M55800A Atmel Corporation, M55800A Datasheet - Page 138

• Manufacturer Part Number: M55800A
• Manufacturer: Atmel Corporation

Specifications of M55800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 176
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 58
• Ext Interrupts: 58
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 72
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

18.3.2
18.3.3
18.3.4
18.3.5
18.3.6
138
AT91M5880A
Synchronous Receiver
Receiver Ready
Parity Error
Framing Error
Time-out
When configured for synchronous operation (SYNC = 1), the receiver samples the RXD signal
on each rising edge of the Baud Rate clock. If a low level is detected, it is considered as a start.
Data bits, parity bit and stop bit are sampled and the receiver waits for the next start bit. See
example in
Figure 18-5. Synchronous Mode: Character Reception
When a complete character is received, it is transferred to the US_RHR and the RXRDY status
bit in US_CSR is set. If US_RHR has not been read since the last transfer, the OVRE status bit
in US_CSR is set.
Each time a character is received, the receiver calculates the parity of the received data bits, in
accordance with the field PAR in US_MR. It then compares the result with the received parity bit.
If different, the parity error bit PARE in US_CSR is set. When the character is completed and as
soon as the character is read, the parity status bit is cleared.
If a character is received with a stop bit at low level and with at least one data bit at high level, a
framing error is generated. This sets FRAME in US_CSR.
This function allows an idle condition on the RXD line to be detected. The maximum delay for
which the USART should wait for a new character to arrive while the RXD line is inactive (high
level) is programmed in US_RTOR (Receiver Time-out). When this register is set to 0, no time-
out is detected. Otherwise, the receiver waits for a first character and then initializes a counter
which is decremented at each bit period and reloaded at each byte reception. When the counter
reaches 0, the TIMEOUT bit in US_CSR is set. The user can restart the wait for a first character
with the STTTO (Start Time-out) bit in US_CR.
Calculation of time-out duration:
Example: 8-bit, parity enabled 1 stop
Sampling
RXD
SCK
Figure
True Start Detection
18-5.
D0
Duration
D1
D2
=
Value 4 BitPeriod
D3
•
D4
•
D5
D6
D7
Parity Bit
1745F–ATARM–06-Sep-07
Stop Bit