M55800A Atmel Corporation, M55800A Datasheet - Page 247

• Manufacturer Part Number: M55800A
• Manufacturer: Atmel Corporation

Specifications of M55800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 176
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 58
• Ext Interrupts: 58
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 72
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 27-1. NWAIT Rising
1745F–ATARM–06-Sep-07
NWAIT
MCKI
NWAIT Setup before MCKI Rising (EBI
In other cases, the following erroneous behavior occurs:
At maximum speed, asserting the NWAIT in the first access cycle is not possible, as the sum of
the timings “MCKI Falling to Chip Select” and “NWAIT setup to MCKI rising” are generally higher
than one half of a clock period. This leads to using at least one standard wait state. However,
this is not sufficient except to perform byte or half-word read accesses. Word and write accesses
require at least two standard wait states.
The following waveforms further explain the issue:
If the NWAIT setup time is satisfied on the first rising edge of MCKI, the behavior is accurate.
The EBI operations are not affected when the NWAIT rises.
If the NWAIT setup time is satisfied on the following edges of MCKI and if at least one standard
wait state remains to be executed, the behavior is accurate. In the following example, the num-
ber of standard wait states is two. The NWAIT setup time on the second rising edge of MCKI
must be met.
– 32-bit read accesses are not managed correctly and the first 16-bit data sampling
– During write accesses of any type, the NWE rises on the rising edge of the last cycle
takes into account only the standard wait states. 16- and 8-bit accesses are not
affected.
as defined by the programmed number of wait states. However, NWAIT assertion
does affect the length of the total access. Only the NWE pulse length is inaccurate.
5
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AT91M5880A
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