M55800A Atmel Corporation, M55800A Datasheet - Page 139
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M55800A
Manufacturer Part Number
M55800A
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.M55800A.pdf
(29 pages)
4.M55800A.pdf
(256 pages)
5.M55800A.pdf
(28 pages)
Specifications of M55800A
Flash (kbytes)
0 Kbytes
Pin Count
176
Max. Operating Frequency
33 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
58
Ext Interrupts
58
Usb Speed
No
Usb Interface
No
Spi
1
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
72
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3/5.0
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- M40800 PDF datasheet #2
- M55800A PDF datasheet #3
- M55800A PDF datasheet #4
- M55800A PDF datasheet #5
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- Download datasheet (5Mb)
18.4
18.4.1
18.5
1745F–ATARM–06-Sep-07
Transmitter
Multi-drop Mode
Time-guard
The transmitter has the same behavior in both synchronous and asynchronous operating
modes. Start bit, data bits, parity bit and stop bits are serially shifted, lowest significant bit first,
on the falling edge of the serial clock. See example in
The number of data bits is selected in the CHRL field in US_MR.
The parity bit is set according to the PAR field in US_MR.
The number of stop bits is selected in the NBSTOP field in US_MR.
When a character is written to US_THR (Transmit Holding), it is transferred to the Shift Register
as soon as it is empty. When the transfer occurs, the TXRDY bit in US_CSR is set until a new
character is written to US_THR. If Transmit Shift Register and US_THR are both empty, the
TXEMPTY bit in US_CSR is set.
The Time-guard function allows the transmitter to insert an idle state on the TXD line between
two characters. The duration of the idle state is programmed in US_TTGR (Transmitter Time-
guard). When this register is set to zero, no time-guard is generated. Otherwise, the transmitter
holds a high level on TXD after each transmitted byte during the number of bit periods pro-
grammed in US_TTGR.
When the field PAR in US_MR equals 11X (binary value), the USART is configured to run in
multi-drop mode. In this case, the parity error bit PARE in US_CSR is set when data is detected
with a parity bit set to identify an address byte. PARE is cleared with the Reset Status Bits Com-
mand (RSTSTA) in US_CR. If the parity bit is detected low, identifying a data byte, PARE is not
set.
The transmitter sends an address byte (parity bit set) when a Send Address Command
(SENDA) is written to US_CR. In this case, the next byte written to US_THR will be transmitted
as an address. After this any byte transmitted will have the parity bit cleared.
Figure 18-6. Synchronous and Asynchronous Modes: Character Transmission
between two characters
Baud Rate
Example: 8-bit, parity enabled 1 stop
Idle state duration
Clock
TXD
Start
Bit
D0
=
Time-guard
D1
value
D2
•
D3
period
Bit
D4
Figure
D5
18-6.
D6
AT91M5880A
D7
Parity
Bit
Stop
Bit
139
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