M42800A Atmel Corporation, M42800A Datasheet - Page 97

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

ARM DDI 0029G
Access type
Word
Halfword
Byte
For subword reads the value is placed in the ARM register in the least significant bits
regardless of the byte lane used to read the data. For example, a byte read on A[1:0] =
01 in a little-endian system means that the byte is read on bits D[15:8] but is placed in
the ARM register bits [7:0].
Writes
When the ARM7TDMI processor performs a byte or halfword write, the data being
written is replicated across the data bus, as shown in Figure 3-20 on page 3-28. The
memory system can use the most convenient copy of the data.
A writable memory system must be capable of performing a write to any single byte in
the memory system. This capability is required by the ARM C Compiler and the debug
tool chain.
Note
MAS[1:0]
10
01
01
00
00
00
00
Copyright © 1994-2001. All rights reserved.
A[1:0]
XX
0X
1X
00
01
10
11
Little-endian BIGEND = 0
D[31:0]
D[15:0]
D[31:16]
D[7:0]
D[15:8]
D[23:16]
D[31:24]
Big-endian BIGEND = 1
D[31:0]
D[31:16]
D[15:0]
D[31:24]
D[23:16]
D[15:8]
D[7:0]
Table 3-7 Read accesses
Memory Interface
3-27