M42800A Atmel Corporation, M42800A Datasheet - Page 167
M42800A
Manufacturer Part Number
M42800A
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.M42800A.pdf
(224 pages)
4.M42800A.pdf
(27 pages)
Specifications of M42800A
Flash (kbytes)
0 Kbytes
Pin Count
144
Max. Operating Frequency
33 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
54
Usb Speed
No
Usb Interface
No
Spi
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3/5.0
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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6.16
ARM DDI 0029G
ready
not ready
Coprocessor register transfer, load from coprocessor
Cycle
1
2
3
-
1
2
•
b
b+1
b+2
Address
pc+8
pc+12
pc+12
pc+12
pc+8
pc+8
pc+8
pc+8
pc+12
pc+12
pc+12
The busy-wait cycles are similar to those described in Coprocessor data transfer from
memory to coprocessor on page 6-21, but the transfer is limited to one word, and the
ARM7TDMI core puts the data into the destination register in the third cycle. The third
cycle can be merged with the next prefetch cycle into one memory N-cycle as with all
processor register load instructions.
The cycle timings are listed in Table 6-19 where:
•
Coprocessor register transfer operations are not available in Thumb state.
b represents the busy cycles.
Note
MAS
[1:0]
2
2
2
2
2
2
2
2
2
Copyright © 1994-2001. All rights reserved.
Table 6-19 Coprocessor register transfer, load from coprocessor
nRW
0
0
0
0
0
0
0
0
0
Data
(pc+8)
CPdata
-
(pc+8)
-
-
-
CPdata
-
nMREQ
1
1
0
1
1
1
1
1
0
SEQ
1
0
1
0
0
0
1
0
1
nOPC
0
1
1
0
1
1
1
1
1
Instruction Cycle Timings
nCPI
0
1
1
0
0
0
0
1
1
CPA
0
1
-
0
0
0
0
1
-
CPB
0
1
-
1
1
1
0
1
-
6-25
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