M42800A Atmel Corporation, M42800A Datasheet - Page 76
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M42800A
Manufacturer Part Number
M42800A
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.M42800A.pdf
(224 pages)
4.M42800A.pdf
(27 pages)
Specifications of M42800A
Flash (kbytes)
0 Kbytes
Pin Count
144
Max. Operating Frequency
33 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
54
Usb Speed
No
Usb Interface
No
Spi
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3/5.0
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Memory Interface
3.3.2
3-6
Sequential cycles
The ARM7TDMI processor can perform back-to-back, nonsequential memory cycles.
This happens, for example, when an
memory controller for the ARM7TDMI core, and your memory system is unable to
cope with this case, use the nWAIT signal to extend the bus cycle to allow sufficient
cycles for the memory system. See Stretching access times on page 3-29.
Sequential cycles are used to perform burst transfers on the bus. This information can
be used to optimize the design of a memory controller interfacing to a burst memory
device, such as a DRAM.
During a sequential cycle, the ARM7TDMI processor requests a memory location that
is part of a sequential burst. For the first cycle in the burst, the address can be the same
as the previous internal cycle. Otherwise the address is incremented from the previous
cycle:
•
•
Bursts of byte accesses are not possible.
A burst always starts with an N-cycle or a merged IS-cycle (see Nonsequential cycles
on page 3-5), and continues with S-cycles. A burst comprises transfers of the same type.
The A[31:0] signal increments during the burst. The other address class signals are
unaffected by a burst.
for a burst of word accesses, the address is incremented by 4 bytes
for a burst of halfword accesses, the address is incremented by 2 bytes.
nMREQ
D[31:0]
A[31:0]
Copyright © 1994-2001. All rights reserved.
MCLK
nRAS
nCAS
SEQ
instruction is executed. If you are designing a
Figure 3-2 Nonsequential memory cycle
N-cycle
a
ARM DDI 0029G
S-cycle
a+4
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