M42800A Atmel Corporation, M42800A Datasheet - Page 13
M42800A
Manufacturer Part Number
M42800A
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.M42800A.pdf
(224 pages)
4.M42800A.pdf
(27 pages)
Specifications of M42800A
Flash (kbytes)
0 Kbytes
Pin Count
144
Max. Operating Frequency
33 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
54
Usb Speed
No
Usb Interface
No
Spi
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3/5.0
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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List of Figures
ARM7TDMI Technical Reference Manual
ARM DDI 0029G
Figure P-1
Figure 1-1
Figure 1-2
Figure 1-3
Figure 1-4
Figure 1-5
Figure 1-6
Figure 2-1
Figure 2-2
Figure 2-3
Figure 2-4
Figure 2-5
Figure 2-6
Figure 3-1
Figure 3-2
Figure 3-3
Figure 3-4
Figure 3-5
Figure 3-6
Figure 3-7
Figure 3-8
Figure 3-9
Figure 3-10
Key to timing diagram conventions ............................................................................. xx
Instruction pipeline .................................................................................................... 1-3
ARM7TDMI processor block diagram ....................................................................... 1-7
Main processor .......................................................................................................... 1-8
ARM7TDMI processor functional diagram ................................................................ 1-9
ARM instruction set formats .................................................................................... 1-11
Thumb instruction set formats ................................................................................. 1-20
LIttle-endian addresses of bytes and halfwords within words ................................... 2-4
Big-endian addresses of bytes and halfwords within words ...................................... 2-5
Register organization in ARM state ........................................................................... 2-9
Register organization in Thumb state ..................................................................... 2-10
Mapping of Thumb-state registers onto ARM-state registers .................................. 2-11
Program status register format ................................................................................ 2-13
Simple memory cycle ................................................................................................ 3-4
Nonsequential memory cycle .................................................................................... 3-6
Sequential access cycles .......................................................................................... 3-7
Internal cycles ........................................................................................................... 3-8
Merged IS cycle ........................................................................................................ 3-9
Coprocessor register transfer cycles ....................................................................... 3-10
Memory cycle timing ............................................................................................... 3-10
Pipelined addresses ................................................................................................ 3-14
Depipelined addresses ............................................................................................ 3-15
SRAM compatible address timing ........................................................................... 3-16
Copyright © 1994-2001. All rights reserved.
xiii
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