M42800A Atmel Corporation, M42800A Datasheet - Page 177
M42800A
Manufacturer Part Number
M42800A
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.M42800A.pdf
(224 pages)
4.M42800A.pdf
(27 pages)
Specifications of M42800A
Flash (kbytes)
0 Kbytes
Pin Count
144
Max. Operating Frequency
33 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
54
Usb Speed
No
Usb Interface
No
Spi
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3/5.0
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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ARM DDI 0029G
In Figure 7-1 on page 7-4, nWAIT, APE, ALE, and ABE are all HIGH during the cycle
shown. T
to ECLK.
Note
cdel
Symbol
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Copyright © 1994-2001. All rights reserved.
addr
ah
bld
blh
cdel
exd
exh
mdd
mdh
msd
msh
opcd
opch
rwd
rwh
is the delay, on either edge (whichever is greater), from the edge of MCLK
Parameter
MCLKr to address valid
Address hold time from MCLKr
MCLKr to MAS[1:0] and LOCK
MAS[1:0] and LOCK hold from MCLKr
MCLK to ECLK delay
MCLKf to nEXEC valid
nEXEC hold time from MCLKf
MCLKr to nTRANS, nM[4:0], and TBIT valid
nTRANS and nM[4:0] hold time from MCLKr
MCLKf to nMREQ and SEQ valid
nMREQ and SEQ hold time from MCLKf
MCLKr to nOPC valid
nOPC hold time from MCLKr
MCLKr to nRW valid
nRW hold time from MCLKr
Table 7-1 General timing parameters
AC and DC Parameters
Parameter type
Maximum
Minimum
Maximum
Minimum
Maximum
Maximum
Minimum
Minimum
Minimum
Maximum
Minimum
Minimum
Maximum
Maximum
Maximum
7-5
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