M42800A Atmel Corporation, M42800A Datasheet - Page 59
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M42800A
Manufacturer Part Number
M42800A
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.M42800A.pdf
(224 pages)
4.M42800A.pdf
(27 pages)
Specifications of M42800A
Flash (kbytes)
0 Kbytes
Pin Count
144
Max. Operating Frequency
33 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
54
Usb Speed
No
Usb Interface
No
Spi
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3/5.0
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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2.7
2.7.1
ARM DDI 0029G
The program status registers
Condition code flags
31 30 29 28 27 26 25 24 23
N Z C V
The ARM7TDMI processor contains a CPSR and five SPSRs for exception handlers to
use. The program status registers:
•
•
•
The arrangement of bits is shown in Figure 2-6.
To maintain compatibility with future ARM processors, you must not alter any of the
reserved bits. One method of preserving these bits is to use a read-write-modify strategy
when changing the CPSR.
The remainder of this section describes:
•
•
•
The N, Z, C, and V bits are the condition code flags, you can set them by arithmetic and
logical operations. They can also be set by MSR and LDM instructions. The
ARM7TDMI processor tests these flags to determine whether to execute an instruction.
code flags
Condition
hold information about the most recently performed ALU operation
control the enabling and disabling of interrupts
set the processor operating mode.
Condition code flags on page 2-13
Control bits on page 2-14
Reserved bits on page 2-15.
Note
Copyright © 1994-2001. All rights reserved.
•
Overflow
Carry or borrow or extend
Zero
Negative or less than
•
•
Reserved
•
•
Figure 2-6 Program status register format
8
•
7
I
6
F
5
T
Control bits
M4 M3 M2 M1 M0
4
3
Programmer’s Model
2
Mode bits
State bit
FIQ disable
IRQ disable
1
0
2-13
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