ATxmega64A3 Atmel Corporation, ATxmega64A3 Datasheet - Page 430

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ATxmega64A3

Manufacturer Part Number
ATxmega64A3
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATxmega64A3

Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Speed
No
Usb Interface
No
Spi
10
Twi (i2c)
2
Uart
7
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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34.3
34.4
34.5
8077H–AVR–12/09
8077F – 02/09
8077E – 01/09
8077D – 12/08
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Updated
Updated
Updated
Added ADC section
Updated
Updated
Updated data sheet cross-references.
Updated
Updated
Added ADC section
Added DAC section
Updated the front page.
Updated Feature list in
Updated
20.
Added Signtaure Row register description in Memory section, updated signature row summary
with byte addresses.
Updated
Updated lication of BODACT fuse bits in FUSEBYTE5 in
Fuses and Lockbits” on page
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Updated
Updated Overview in
Updated
Updated
Inserted a new section
Updated title of the
Updated
Updated
Updated
”STATUS: Battery Backup Status Register” on page
Table 9-2 on page
”Conversion Result” on page
”Overview” on page
”Capture Channel” on page
Figure 9-5
”Capture Channel” on page
”Production Signature Row” on page 20
”MCUCR – MCU Control Register” on page
”Interrupt Vector Summary - NVM Controller” on page
”Priority Between Channels” on page
”Manually Generating Events” on page 67
”Quadrature Decoder (QDEC)” on page
Figure 13-1 ”General I/O pin functionality.” on page
Table 13-7 ”Event Channel 0 output configurations” on page
Figure 13-10 ”Port override signals and related logic” on page
Table 13-7 on page
External reset characteristics in
”DAC Output model” on page
”Interrupt vector Summary” on page
”ADC Input Model” on page
”Event System” on page
”Memories” on page
”Battery Backup System” on page
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145: Event Channel 0 Output Configurations.
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and inserted
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and
Section 9.4.3 ”External reset” on page
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”Event Routing Network” on page
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Section 4.22 ”Register Summary -
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”User Signature Row” on page
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XMEGA A
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430

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