ATxmega64A3 Atmel Corporation, ATxmega64A3 Datasheet - Page 304

• Manufacturer Part Number: ATxmega64A3
• Manufacturer: Atmel Corporation

Specifications of ATxmega64A3

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

25.16.4
8077H–AVR–12/09
EVCTRL - ADC Event Control Register
Table 25-3.
Notes:
• Bit 3:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 1 – BANDGAP: Bandgap enable
Setting this bit enables the bandgap to prepare for ADC measurement. Note that if any other
functions are using the bandgap already, this bit does not need to be set. This could be when the
internal 1.00V reference is used in ADC or DAC, or if the Brown-out Detector is enabled.
• Bit 0 – TEMPREF: Temperature Reference enable
Setting this bit enables the temperature reference to prepare for ADC measurement.
• Bits 7:6 - SWEEP[1:0]: ADC Channel Sweep
These bits control which ADC channels are included in a channel sweep triggered by the event
system or in free running mode. See
Table 25-4.
• Bits 5:3 - EVSEL[2:0]: event channel input select
These bits define which event channel should trigger which ADC channel. Each setting defines a
group of event channels, where the event channels with the lowest number will trigger ADC
channel 0 and the next event channel will trigger ADC channel 1 and so on. The number of
incoming event in use is defined by the EVACT bits. See
Bit
+0x03
Read/Write
Initial Value
REFSEL[1:0]
SWEEP[1:0]
1. Only available if AREF exist on PORT A.
2. Only available it AREF exist on PORT B.
10
11
00
01
10
11
00
01
(1)
(2)
R/W
7
0
ADC Reference Configuration
ADC Channel Select
SWEEP[1:0]
R/W
6
0
Group Configuration
Group Configuration
INTVCC
AREFB
AREFA
INT1V
0123
R/W
012
5
0
01
0
Table 25-4 on page
EVSEL[2:0]
R/W
4
0
Description
Internal 1.00V
Internal V
External reference from AREF pin on PORT A.
External reference from AREF pin on PORT B.
Active ADC channels for channel sweep
Only ADC channel 0
ADC channels 0 and 1
ADC channels 0, 1, and 2
ADC channels 0, 1, 2, and 3
R/W
3
0
CC
Table 25-5 on page
304.
/1.6
R/W
2
0
EVACT[2:0]
R/W
1
0
XMEGA A
305.
R/W
0
0
EVCTRL
304