ATxmega64A3 Atmel Corporation, ATxmega64A3 Datasheet - Page 191

• Manufacturer Part Number: ATxmega64A3
• Manufacturer: Atmel Corporation

Specifications of ATxmega64A3

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

17.2.1
17.2.2
17.3
17.3.1
8077H–AVR–12/09
Register Description
Clock domains
Interrupts and events
CTRL - Real Time Counter Control Register
The RTC is asynchronous, meaning it operates from a different clock source and independently
of the main System Clock and its derivative clocks such as the Peripheral Clock. For Control and
Count register updates it will take a number of RTC clock and/or Peripheral clock cycles before
an updated register value is available or until a configuration change has effect on the RTC. This
synchronization time is described for each register.
The RTC can generate both interrupts and events. The RTC will give a compare interrupt
request and/or event when the counter value equals the Compare register value. The RTC will
give an overflow interrupt request and/or event when the counter value equals the Period regis-
ter value. The overflow will also reset the counter value to zero.
Due to the asynchronous clock domains event will only will only be generated for every third
overflow or compare if the period register is zero. If the period register is one, events will only be
generated for every second overflow or compare. When the period register is equal to or above
two, events will trigger at every overflow or compare just as the interrupt request.
• Bits 7:3 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bits 2:0 - PRESCALER[2:0]: RTC Clock Prescaling factor
These bits define the prescaling factor for the RTC clock before the counter according to
17-1 on page
Table 17-1.
Bit
+0x00
Read/Write
Initial Value
PRESCALER[2:0]
000
001
010
011
100
101
110
111
191.
R
7
0
-
Real Time Counter Clock prescaling factor
R
6
0
-
Group Configuration
5
R
0
-
DIV1024
DIV256
DIV16
DIV64
DIV1
DIV2
DIV8
OFF
4
R
0
-
R
3
0
-
RTC clock prescaling
No clock source, RTC stopped
RTC clock / 1 (No prescaling)
RTC clock / 2
RTC clock / 8
RTC clock / 16
RTC clock / 64
RTC clock / 256
RTC clock / 1024
R/W
2
0
PRESCALER[2:0]
R/W
1
0
XMEGA A
R/W
0
0
CTRL
Table
191