ATmega8 Atmel Corporation, ATmega8 Datasheet - Page 94

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ATmega8

Manufacturer Part Number
ATmega8
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATmega8

Flash (kbytes)
8 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
23
Ext Interrupts
2
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
1
Pwm Channels
3
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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Timer/Counter
Timing Diagrams
94
ATmega8(L)
output will be continuously low and if set equal to TOP the output will be set to high for non-
inverted PWM mode. For inverted PWM the output will have the opposite logic values.
If OCR1A is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A output
will toggle with a 50% duty cycle.
The Timer/Counter is a synchronous design and the timer clock (clk
clock enable signal in the following figures. The figures include information on when Interrupt
Flags are set, and when the OCR1x Register is updated with the OCR1x buffer value (only for
modes utilizing double buffering).
Figure 41. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling
Figure 42
Figure 42. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f
Figure 43 on page 95
phase and frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The tim-
TCNTn
OCRnx
OCRnx
OCFnx
TCNTn
OCFnx
(clk
(clk
clk
clk
clk
clk
I/O
I/O
I/O
Tn
I/O
Tn
/1)
/8)
shows the same timing data, but with the prescaler enabled.
OCRnx - 1
shows the count sequence close to TOP in various modes. When using
OCRnx - 1
Figure 41
OCRnx
shows a timing diagram for the setting of OCF1x.
OCRnx
OCRnx Value
OCRnx Value
OCRnx + 1
OCRnx + 1
T1
) is therefore shown as a
clk_I/O
OCRnx + 2
OCRnx + 2
2486Z–AVR–02/11
/8)

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