ATmega8 Atmel Corporation, ATmega8 Datasheet - Page 138

• Manufacturer Part Number: ATmega8
• Manufacturer: Atmel Corporation

Specifications of ATmega8

• Flash (kbytes): 8 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 23
• Ext Interrupts: 2
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Parity Generator
Disabling the
Transmitter
Data Reception –
The USART
Receiver
Receiving Frames with
5 to 8 Data Bits
138
ATmega8(L)
UDR in order to clear UDRE or disable the Data Register empty Interrupt, otherwise a new inter-
rupt will occur once the interrupt routine terminates.
The Transmit Complete (TXC) Flag bit is set one when the entire frame in the transmit Shift Reg-
ister has been shifted out and there are no new data currently present in the transmit buffer. The
TXC Flag bit is automatically cleared when a transmit complete interrupt is executed, or it can be
cleared by writing a one to its bit location. The TXC Flag is useful in half-duplex communication
interfaces (like the RS485 standard), where a transmitting application must enter Receive mode
and free the communication bus immediately after completing the transmission.
When the Transmit Compete Interrupt Enable (TXCIE) bit in UCSRB is set, the USART Transmit
Complete Interrupt will be executed when the TXC Flag becomes set (provided that global inter-
rupts are enabled). When the transmit complete interrupt is used, the interrupt handling routine
does not have to clear the TXC Flag, this is done automatically when the interrupt is executed.
The Parity Generator calculates the parity bit for the serial frame data. When parity bit is enabled
(UPM1 = 1), the Transmitter control logic inserts the parity bit between the last data bit and the
first stop bit of the frame that is sent.
The disabling of the Transmitter (setting the TXEN to zero) will not become effective until ongo-
ing and pending transmissions are completed (that is, when the Transmit Shift Register and
Transmit Buffer Register do not contain data to be transmitted). When disabled, the Transmitter
will no longer override the TxD pin.
The USART Receiver is enabled by writing the Receive Enable (RXEN) bit in the UCSRB Regis-
ter to one. When the Receiver is enabled, the normal pin operation of the RxD pin is overridden
by the USART and given the function as the Receiver’s serial input. The baud rate, mode of
operation and frame format must be set up once before any serial reception can be done. If syn-
chronous operation is used, the clock on the XCK pin will be used as transfer clock.
The Receiver starts data reception when it detects a valid start bit. Each bit that follows the start
bit will be sampled at the baud rate or XCK clock, and shifted into the Receive Shift Register until
the first stop bit of a frame is received. A second stop bit will be ignored by the Receiver. When
the first stop bit is received (that is, a complete serial frame is present in the Receive Shift Reg-
ister), the contents of the Shift Register will be moved into the receive buffer. The receive buffer
can then be read by reading the UDR I/O location.
The following code example shows a simple USART receive function based on polling of the
Receive Complete (RXC) Flag. When using frames with less than eight bits the most significant
2486Z–AVR–02/11