ATmega8 Atmel Corporation, ATmega8 Datasheet - Page 131
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ATmega8
Manufacturer Part Number
ATmega8
Description
Manufacturer
Atmel Corporation
Specifications of ATmega8
Flash (kbytes)
8 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
23
Ext Interrupts
2
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
1
Pwm Channels
3
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Internal Clock
Generation – The
Baud Rate Generator
2486Z–AVR–02/11
Figure 62. Clock Generation Logic, Block Diagram
Signal description:
Internal clock generation is used for the asynchronous and the Synchronous Master modes of
operation. The description in this section refers to
The USART Baud Rate Register (UBRR) and the down-counter connected to it function as a
programmable prescaler or baud rate generator. The down-counter, running at system clock
(fosc), is loaded with the UBRR value each time the counter has counted down to zero or when
the UBRRL Register is written. A clock is generated each time the counter reaches zero. This
clock is the baud rate generator clock output (= fosc/(UBRR+1)). The Transmitter divides the
baud rate generator clock output by 2, 8, or 16 depending on mode. The baud rate generator
output is used directly by the Receiver’s clock and data recovery units. However, the recovery
units use a state machine that uses 2, 8, or 16 states depending on mode set by the state of the
UMSEL, U2X and DDR_XCK bits.
Table 52 on page 132
for calculating the UBRR value for each mode of operation using an internally generated clock
source.
txclk
rxclk
xcki
xcko
fosc
DDR_XCK
XCK
Pin
Transmitter clock. (Internal Signal)
Receiver base clock. (Internal Signal)
Input from XCK pin (internal Signal). Used for synchronous slave operation
Clock output to XCK pin (Internal Signal). Used for synchronous master
operation
XTAL pin frequency (System Clock)
xcko
xcki
OSC
Down-Counter
contains equations for calculating the baud rate (in bits per second) and
Prescaling
Register
UBRR
Sync
UBRR+1
fosc
Detector
UCPOL
Edge
/ 2
Figure
62.
/ 4
/ 2
DDR_XCK
ATmega8(L)
U2X
0
1
0
1
0
1
1
0
UMSEL
txclk
rxclk
131