ATmega8 Atmel Corporation, ATmega8 Datasheet - Page 104

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ATmega8

Manufacturer Part Number
ATmega8
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATmega8

Flash (kbytes)
8 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
23
Ext Interrupts
2
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
1
Pwm Channels
3
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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Counter Unit
104
ATmega8(L)
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.
46
Figure 46. Counter Unit Block Diagram
Signal description (internal signals):
Depending on the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clk
selected by the clock select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the
timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of
whether clk
count operations.
The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in
the Timer/Counter Control Register (TCCR2). There are close connections between how the
counter behaves (counts) and how waveforms are generated on the Output Compare Output
OC2. For more details about advanced counting sequences and waveform generation, see
“Modes of Operation” on page
The Timer/Counter Overflow (TOV2) Flag is set according to the mode of operation selected by
the WGM21:0 bits. TOV2 can be used for generating a CPU interrupt.
count
direction
clear
clk
TOP
BOTTOM
shows a block diagram of the counter and its surrounding environment.
T2
DATA BUS
T2
TCNTn
Increment or decrement TCNT2 by 1
Selects between increment and decrement
Clear TCNT2 (set all bits to zero)
Timer/Counter clock
Signalizes that TCNT2 has reached maximum value
Signalizes that TCNT2 has reached minimum value (zero)
is present or not. A CPU write overrides (has priority over) all counter clear or
T2
). clk
direction
count
BOTTOM
clear
108.
T2
can be generated from an external or internal clock source,
Control Logic
TOP
TOVn
(Int. Req.)
clk
Tn
Prescaler
Oscillator
T/C
clk
I/O
2486Z–AVR–02/11
TOSC2
TOSC1
Figure

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