ATmega8 Atmel Corporation, ATmega8 Datasheet - Page 126

• Manufacturer Part Number: ATmega8
• Manufacturer: Atmel Corporation

Specifications of ATmega8

• Flash (kbytes): 8 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 23
• Ext Interrupts: 2
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

SPI Status Register –
SPSR
126
ATmega8(L)
• Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic
zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared,
and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mas-
ter mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low
when idle. Refer to
CPOL functionality is summarized below:
Table 48. CPOL Functionality
• Bit 2 – CPHA: Clock Phase
The settings of the clock phase bit (CPHA) determine if data is sampled on the leading (first) or
trailing (last) edge of SCK. Refer to
example. The CPHA functionality is summarized below:
Table 49. CPHA Functionality
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have
no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency f
shown in the following table:
Table 50. Relationship Between SCK and the Oscillator Frequency
Bit
Read/Write
Initial Value
SPI2X
CPOL
CPHA
0
0
0
0
1
1
1
1
0
1
0
1
SPIF
R
7
0
Figure 59 on page 128
WCOL
SPR1
R
6
0
0
0
1
1
0
0
1
1
Leading Edge
Leading Edge
R
5
–
0
Sample
Falling
Rising
Setup
Figure 59 on page 128
SPR0
R
0
4
–
0
1
0
1
0
1
0
1
and
3
–
R
0
Figure 60 on page 128
SCK Frequency
f
f
f
f
f
f
f
f
osc
osc
osc
osc
osc
osc
osc
osc
/
/
/
/
/
/
/
/
4
16
64
128
2
8
32
64
R
2
–
0
and
Trailing Edge
Trailing Edge
R
1
–
0
Figure 60 on page 128
Sample
Falling
Rising
Setup
SPI2X
R/W
0
0
for an example. The
SPSR
2486Z–AVR–02/11
for an
osc
is