ATmega32A Atmel Corporation, ATmega32A Datasheet - Page 36

• Manufacturer Part Number: ATmega32A
• Manufacturer: Atmel Corporation

Specifications of ATmega32A

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 32
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

9.8.4
9.8.5
9.8.6
9.8.7
8155C–AVR–02/11
Internal Voltage Reference
Watchdog Timer
Port Pins
JTAG Interface and On-chip Debug System
The Internal Voltage Reference will be enabled when needed by the Brown-out Detector, the
Analog Comparator or the ADC. If these modules are disabled as described in the sections
above, the internal voltage reference will be disabled and it will not be consuming power. When
turned on again, the user must allow the reference to start up before the output is used. If the
reference is kept on in sleep mode, the output can be used immediately. Refer to
age Reference” on page 36
If the Watchdog Timer is not needed in the application, this module should be turned off. If the
Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume
power. In the deeper sleep modes, this will contribute significantly to the total current consump-
tion. Refer to
When entering a sleep mode, all port pins should be configured to use minimum power. The
most important thing is then to ensure that no pins drive resistive loads. In sleep modes where
the both the I/O clock (clk
device will be disabled. This ensures that no power is consumed by the input logic when not
needed. In some cases, the input logic is needed for detecting wake-up conditions, and it will
then be enabled. Refer to the section
details on which pins are enabled. If the input buffer is enabled and the input signal is left floating
or have an analog signal level close to V
The TDO pin is left floating when the JTAG interface is enabled while the JTAG TAP controller is
not shifting data. If the hardware connected to the TDO pin does not pull up the logic level,
power consumption will increase. Note that the TDI pin for the next device in the scan chain con-
tains a pull-up that avoids this problem. Writing the JTD bit in the MCUCSR register to one or
leaving the JTAG fuse unprogrammed disables the JTAG interface.
• If the On-chip debug system is enabled by the OCDEN Fuse and the chip enter Power down
• Disable OCDEN Fuse.
• Disable JTAGEN Fuse.
• Write one to the JTD bit in MCUCSR.
or Power save sleep mode, the main clock source remains enabled. In these sleep modes,
this will contribute significantly to the total current consumption. There are three alternative
ways to avoid this:
“Watchdog Timer” on page 36
I/O
for details on the start-up time.
) and the ADC clock (clk
“Digital Input Enable and Sleep Modes” on page 54
CC
/2, the input buffer will use excessive power.
for details on how to configure the Watchdog Timer.
ADC
) are stopped, the input buffers of the
ATmega32A
“Internal Volt-
for
36