ATmega32A Atmel Corporation, ATmega32A Datasheet - Page 177
![no-image](/images/manufacturer_photos/0/0/79/atmel_corporation_sml.jpg)
ATmega32A
Manufacturer Part Number
ATmega32A
Description
Manufacturer
Atmel Corporation
Specifications of ATmega32A
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
3
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA32A
Manufacturer:
Atmel
Quantity:
150
Part Number:
ATMEGA32A
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATmega32A-AU
Manufacturer:
ATMEL
Quantity:
5 600
Part Number:
ATmega32A-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATmega32A-AUR
Manufacturer:
SMD
Quantity:
5
Part Number:
ATmega32A-MU
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Company:
Part Number:
ATmega32A-PU
Manufacturer:
ATMEL
Quantity:
3 000
Company:
Part Number:
ATmega32A-PU
Manufacturer:
Atmel
Quantity:
26 792
20. Two-wire Serial Interface
20.1
20.2
8155C–AVR–02/11
Features
Two-wire Serial Interface Bus Definition
•
•
•
•
•
•
•
•
•
•
The Two-wire Serial Interface (TWI) is ideally suited for typical microcontroller applications. The
TWI protocol allows the systems designer to interconnect up to 128 different devices using only
two bi-directional bus lines, one for clock (SCL) and one for data (SDA). The only external hard-
ware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. All
devices connected to the bus have individual addresses, and mechanisms for resolving bus
contention are inherent in the TWI protocol.
Figure 20-1. TWI Bus Interconnection
Simple Yet Powerful and Flexible Communication Interface, Only Two Bus Lines Needed
Both Master and Slave Operation Supported
Device Can Operate as Transmitter or Receiver
7-bit Address Space allows up to 128 Different Slave Addresses
Multi-master Arbitration Support
Up to 400kHz Data Transfer Speed
Slew-rate Limited Output Drivers
Noise Suppression Circuitry Rejects Spikes on Bus Lines
Fully Programmable Slave Address with General Call Support
Address Recognition causes Wake-up when AVR is in Sleep Mode
SDA
SCL
Device 1
Device 2
Device 3
........
Device n
V
CC
ATmega32A
R1
R2
177