ATmega16HVB Atmel Corporation, ATmega16HVB Datasheet - Page 96

• Manufacturer Part Number: ATmega16HVB
• Manufacturer: Atmel Corporation

Specifications of ATmega16HVB

• Flash (kbytes): 16 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 8 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 17
• Ext Interrupts: 15
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1.9
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 4.0 to 25
• Operating Voltage (vcc): 4.0 to 25
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

17.10.6
17.10.7
96
ATmega16HVB/32HVB
TIMSKn – Timer/Counter n Interrupt Mask Register
TIFRn – Timer/Counter n Interrupt Flag Register
In 16-bit mode the OCRnB register contains the high byte of the 16-bit Output Compare Regis-
ter. To ensure that both the high and the low bytes are written simultaneously when the CPU
writes to these registers, the access is performed using an 8-bit temporary high byte register
(TEMP). This temporary register is shared by all the other 16-bit registers. See
ters in 16-bit mode” on page
• Bit 3 – ICIEn: Timer/Counter n Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter n Input Capture interrupt is enabled. The corresponding Interrupt
Vector (see
• Bit 2 – OCIEnB: Timer/Counter n Output Compare Match B Interrupt Enable
When the OCIEnB bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if
a Compare Match in Timer/Counter occurs, that is, when the OCFnB bit is set in the
Timer/Counter Interrupt Flag Register – TIFRn.
• Bit 1 – OCIEnA: Timer/Counter n Output Compare Match A Interrupt Enable
When the OCIEnA bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter n Compare Match A interrupt is enabled. The corresponding interrupt is executed
if a Compare Match in Timer/Counter n occurs, that is, when the OCFnA bit is set in the
Timer/Counter n Interrupt Flag Register – TIFRn.
• Bit 0 – TOIEn: Timer/Counter n Overflow Interrupt Enable
When the TOIEn bit is written to one, and the I-bit in the Status Register is set, the Timer/Coun-
ter n Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in
Timer/Counter n occurs, that is, when the TOVn bit is set in the Timer/Counter n Interrupt Flag
Register – TIFRn.
• Bits 3 – ICFn: Timer/Counter n Input Capture Flag
This flag is set when a capture event occurs, according to the setting of ICENn, ICESn and ICSn
bits in the TCCRnA Register.
ICFn is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively,
ICFn can be cleared by writing a logic one to its bit location.
Bit
(0x6E)(0x6F)
Read/Write
Initial Value
Bit
0x15 (0x35)
Read/Write
Initial Value
”Interrupts” on page
R
R
7
–
0
7
–
0
R
R
6
–
0
6
–
0
90.
52) is executed when the ICFn flag, located in TIFRn, is set.
R
5
–
R
0
5
–
0
R
R
4
–
0
4
–
0
ICIEn
ICFn
R/W
R/W
3
0
3
0
OCIEnB
OCFnB
R/W
R/W
2
0
2
0
OCIEnA
OCFnA
R/W
R/W
1
0
1
0
”Accessing regis-
TOIEn
TOVn
R/W
R
0
0
0
0
8042D–AVR–10/11
TIMSKn
TIFRn