ATmega16HVB Atmel Corporation, ATmega16HVB Datasheet - Page 60
ATmega16HVB
Manufacturer Part Number
ATmega16HVB
Description
Manufacturer
Atmel Corporation
Specifications of ATmega16HVB
Flash (kbytes)
16 Kbytes
Pin Count
44
Max. Operating Frequency
8 MHz
Cpu
8-bit AVR
# Of Touch Channels
8
Hardware Qtouch Acquisition
No
Max I/o Pins
17
Ext Interrupts
15
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
1.9
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
4.0 to 25
Operating Voltage (vcc)
4.0 to 25
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
4
Input Capture Channels
2
32khz Rtc
No
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATmega16HVB-8X3
Manufacturer:
LT
Quantity:
51
Part Number:
ATmega16HVB-8X3
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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13.2.4
13.2.5
13.2.6
60
ATmega16HVB/32HVB
PCICR – Pin Change Interrupt Control Register
PCIFR – Pin Change Interrupt Flag Register
PCMSK1 – Pin Change Mask Register 1
• Bits 7:2 – Reserved
These bits are reserved in the Atmel ATmega16HVB/32HVB, and will always read as zero.
• Bit 1 – PCIE1: Pin Change Interrupt Enable 1
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 1 is enabled. Any change on any enabled PCINT11..4 pin will cause an inter-
rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1
Interrupt Vector. PCINT11..4 pins are enabled individually by the PCMSK1 Register.
• Bit 0 – PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 0 is enabled. Any change on any enabled PCINT3..0 pin will cause an interrupt.
The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Interrupt
Vector. PCINT3..0 pins are enabled individually by the PCMSK0 Register.
• Bits 7:2 – Reserved
These bits are reserved in the ATmega16HVB/32HVB, and will always read as zero.
• Bit 1 – PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT11..4 pin triggers an interrupt request, PCIF1 becomes set
(one). If the I-bit in SREG and the PCIE1 bit in EIMSK are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
• Bit 0 – PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT3:0 pin triggers an interrupt request, PCIF0 becomes set
(one). If the I-bit in SREG and the PCIE0 bit in EIMSK are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
Bit
(0x68)
Read/Write
Initial Value
Bit
0x1B (0x3B)
Read/Write
Initial Value
Bit
(0x6C)
Read/Write
Initial Value
PCINT11
R/W
7
0
R
R
7
–
0
7
–
0
PCINT10
R/W
6
0
R
R
6
–
0
6
–
0
PCINT9
R/W
5
0
R
R
5
–
0
5
–
0
PCINT8
R/W
4
0
R
R
4
–
0
4
–
0
PCINT7
R/W
3
0
R
R
3
–
0
3
–
0
PCINT6
R/W
2
0
R
R
2
–
0
2
–
0
PCINT5
PCIE1
PCIF1
R/W
R/W
R/W
1
0
1
0
1
0
PCINT4
PCIE0
PCIF0
R/W
R/W
R/W
0
0
0
0
0
0
8042D–AVR–10/11
PCMSK1
PCICR
PCIFR
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