ATmega16HVB Atmel Corporation, ATmega16HVB Datasheet - Page 33

• Manufacturer Part Number: ATmega16HVB
• Manufacturer: Atmel Corporation

Specifications of ATmega16HVB

• Flash (kbytes): 16 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 8 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 17
• Ext Interrupts: 15
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1.9
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 4.0 to 25
• Operating Voltage (vcc): 4.0 to 25
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

9.8.4
8042D–AVR–10/11
OSICSR – Oscillator sampling interface control and Status Register
• Bit 7 – CLKPCE: Clock Prescaler change enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE
bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is
cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the
CLKPCE bit within this time-out period does neither extend the time-out period, or clear the CLK-
PCE bit.
• Bit 1:0 – CLKPS[1:0]: Clock Prescaler select Bit[1:0]
These bits define the division factor between the selected clock source and the internal system
clock. These bits can be written run-time to vary the clock frequency to suit the application
requirements. As the divider divides the master clock input to the MCU, the speed of all synchro-
nous peripherals is reduced when a division factor is used. The division factors are given in
Table
VADC conversion.
The CKDIV8 Fuse (see
If CKDIV8 is unprogrammed, the CLKPS bits will be reset to “00”. If CKDIV8 is programmed,
CLKPS bits are reset to “11”, giving a division factor of eight at startup (default factory setting).
Note that any value can be written to the CLKPS bits, regardless of the CKDIV8 Fuse setting.
Table 9-4.
Table 9-5.
Note:
Bit
0x17 (0x37)
Read/Write
Initial Value
9-4. Note that writing to the System Clock Prescaler Select bits will abort any ongoing
1. When changing Prescaler value, the VADC Prescaler will automatically change frequency of
the VADC clock and abort any ongoing conversion.
CLKPS1
CLKPS1
System clock prescaler select.
VADC Clock prescaling
0
0
1
1
0
0
1
1
R
7
–
0
Table 30-3 on page
R
6
–
0
R
5
–
0
(1)
.
OSISEL0
R/W
CLKPS0
CLKPS0
4
0
205) determines the initial value of the CLKPS bits.
0
1
0
1
0
1
0
1
ATmega16HVB/32HVB
R
3
–
0
R
2
–
0
OSIST
VADC division factor
Clock division factor
R
1
0
OSIEN
8
4
2
1
1
2
4
8
R/W
0
0
OSICSR
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