ATmega16HVB Atmel Corporation, ATmega16HVB Datasheet - Page 208
ATmega16HVB
Manufacturer Part Number
ATmega16HVB
Description
Manufacturer
Atmel Corporation
Specifications of ATmega16HVB
Flash (kbytes)
16 Kbytes
Pin Count
44
Max. Operating Frequency
8 MHz
Cpu
8-bit AVR
# Of Touch Channels
8
Hardware Qtouch Acquisition
No
Max I/o Pins
17
Ext Interrupts
15
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
1.9
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
4.0 to 25
Operating Voltage (vcc)
4.0 to 25
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
4
Input Capture Channels
2
32khz Rtc
No
Calibrated Rc Oscillator
Yes
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
ATmega16HVB-8X3
Manufacturer:
LT
Quantity:
51
Part Number:
ATmega16HVB-8X3
Manufacturer:
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Quantity:
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30.6.1
208
ATmega16HVB/32HVB
Serial programming algorithm
Figure 30-1. Serial programming and verify.
Table 30-10. Pin mapping serial programming.
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on OSCSEL Fuses, a valid clock must be present. The minimum low and high peri-
ods for the serial clock (SCK) input are defined as follows:
Low: > 2.2 CPU clock cycles for f
High: > 2.2 CPU clock cycles for f
When writing serial data to the Atmel ATmega16HVB/32HVB, data is clocked on the rising edge
of SCK.
When reading data from the ATmega16HVB/32HVB, data is clocked on the falling edge of SCK.
See
To program and verify the ATmega16HVB/32HVB in the Serial Programming mode, the follow-
ing sequence is recommended (see four byte instruction formats in
1. Power-up sequence:
2. Wait for at least 20ms and enable serial programming by sending the Programming
Make sure the chip is started as explained in
connect” on page 43
grammer can not guarantee that SCK is held low during power-up. In this case, RESET
must be given a positive pulse of at least two CPU clock cycles duration after SCK has
been set to “0”.
Enable serial instruction to pin MOSI.
”Serial programming characteristics” on page 234
Symbol
MOSI
MISO
SCK
MOSI
MOSI
MISO
MISO
SCK
SCK
while RESET and SCK are set to “0”. In some systems, the pro-
Pins
PB5
PB6
PB7
ck
ck
<12MHz, 3 CPU clock cycles for f
<12MHz, 3 CPU clock cycles for f
RESET
RESET
GND
GND
I/O
Section 11.2.1 ”Power-on reset and charger
O
I
I
for timing details.
V
V
FET
FET
+4.0V - 25.0V
+4.0V - 25.0V
Table 30-12 on page
Serial Data out
ck
ck
Serial Data in
Description
Serial Clock
>=12MHz
>=12MHz
8042D–AVR–10/11
210):
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