ATmega16HVB Atmel Corporation, ATmega16HVB Datasheet - Page 128
ATmega16HVB
Manufacturer Part Number
ATmega16HVB
Description
Manufacturer
Atmel Corporation
Specifications of ATmega16HVB
Flash (kbytes)
16 Kbytes
Pin Count
44
Max. Operating Frequency
8 MHz
Cpu
8-bit AVR
# Of Touch Channels
8
Hardware Qtouch Acquisition
No
Max I/o Pins
17
Ext Interrupts
15
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
1.9
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
4.0 to 25
Operating Voltage (vcc)
4.0 to 25
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
4
Input Capture Channels
2
32khz Rtc
No
Calibrated Rc Oscillator
Yes
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
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Manufacturer:
LT
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22.4
22.4.1
128
Register description
ATmega16HVB/32HVB
CHGDCSR – Charger Detect Control and Status Register
•
• Bit 7:5 – Reserved
These bits are reserved and will always read as zero.
• Bit 4 – BATTPVL: BATT pin Voltage Level
BATTPVL will read one as long when the Charger Detect module is enabled and the BATT pin
voltage is above the VPOT level. Otherwise the BATTPVL will read zero.
• Bit 3:2 – CHGDISC[1:0]: Charger Detect Interrupt Sense Control
Edges in the CHARGER_PRESENT signal shown in
vate a Charger Detect Interrupt if the SREG I-flag and the interrupt enable bit in CHGDCSR are
set. By writing the CHGDISC bits to the values shown in
interrupt is configured. When changing the CHGDISC bits, an interrupt can occur. Therefore, it is
recommended to first disable the Interrupt by clearing its CHGDIE bit in the CHGDICSR Regis-
ter. Finally, the Charger Detect interrupt flag should be cleared by writing a logical one to
CHGDIF bit before the interrupt is re-enabled.
Table 22-1.
• Bit 1 – CHGDIF: Charger Detect Interrupt Flag
Depending on the configuration of the CHGDISC bits in the CHGDCSR, this bit is set when a
charger is either connected or disconnected. The Charger Detect Interrupt is executed if the
CHGDIE bit and the I-bit in SREG are set. This bit is cleared by hardware when executing the
corresponding interrupt handling vector or alternatively by writing a logical one to the CHGDIF. It
is recommended to write this bit to one when setting CHGDIE.
• Bit 0 – CHGDIE: Charger Detect Interrupt Enable
When the CHGDIE bit is set (one), and the I-bit in the Status Register is set (one), the Charger
Detect Interrupt is enabled.
Bit
(0xD4)
Read/Write
Initial Value
When disabling the Charge-FET the Charger Detect module is automatically enabled and a
charger appear to be connected
CHGISC[1:0]
R
7
–
0
00
01
10
11
Charger Detect Interrupt Sense Control.
R
6
–
0
R
5
–
0
BATTPVL
Detection
Charger Connect
Charger Disconnect
Charger Connect/Disconnect
None
R
4
0
CHGDISC1
R/W
3
0
CHGDISC0
Figure 22-1 on page 126
R/W
2
0
Table 22-1
CHGDIF
R/W
1
0
the condition generating
CHGDIE
R/W
are used to acti-
0
0
8042D–AVR–10/11
CHGDCSR
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