AT90USB162 Atmel Corporation, AT90USB162 Datasheet - Page 258

• Manufacturer Part Number: AT90USB162
• Manufacturer: Atmel Corporation

Specifications of AT90USB162

• Flash (kbytes): 16 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 22
• Ext Interrupts: 21
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 5
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

25.8.1
258
AT90USB82/162
Serial Programming Algorithm
Notes:
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
When writing serial data to the AT90USB82/162, data is clocked on the rising edge of SCK.
When reading data from the AT90USB82/162, data is clocked on the falling edge of SCK. See
Figure 25-11
To program and verify the AT90USB82/162 in the serial programming mode, the following
sequence is recommended (See four byte instruction formats in
1. Power-up sequence:
2. Wait for at least 20 ms and enable serial programming by sending the Programming
3. The serial programming instructions will not work if the communication is out of syn-
4. The Flash is programmed one page at a time. The memory page is loaded one byte at
Apply power between V
tems, the programmer can not guarantee that SCK is held low during power-up. In this
case, RESET must be given a positive pulse of at least two CPU clock cycles duration
after SCK has been set to “0”.
Enable serial instruction to pin PDI.
chronization. When in sync. the second byte (0x53), will echo back when issuing the
third byte of the Programming Enable instruction. Whether the echo is correct or not, all
four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give
RESET a positive pulse and issue a new Programming Enable command.
a time by supplying the 7 LSB of the address and data together with the Load Program
1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the
2. V
XTAL1 pin.
CC
for timing details.
- 0.3V < AVCC < V
CC
PDO
SCK
PDI
ck
ck
and GND while RESET and SCK are set to “0”. In some sys-
CC
< 12 MHz, 3 CPU clock cycles for f
< 12 MHz, 3 CPU clock cycles for f
+ 0.3V, however, AVCC should always be within 1.8 - 5.5V
XTAL1
RESET
GND
AVCC
VCC
+1.8 - 5.5V
+1.8 - 5.5V
Table
(2)
ck
ck
25-16):
>= 12 MHz
>= 12 MHz
7707F–AVR–11/10