AT90USB162 Atmel Corporation, AT90USB162 Datasheet - Page 181

• Manufacturer Part Number: AT90USB162
• Manufacturer: Atmel Corporation

Specifications of AT90USB162

• Flash (kbytes): 16 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 22
• Ext Interrupts: 21
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 5
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

18.6.4
Table 18-3.
18.6.5
18.7
7707F–AVR–11/10
UMSELn1
0
0
1
1
AVR USART MSPIM vs.
AVR SPI
USART MSPIM Control and Status Register n C - UCSRnC
USART MSPIM Baud Rate Registers - UBRRnL and UBRRnH
UMSELn Bits Settings
• Bit 7:6 - UMSELn1:0: USART Mode Select
These bits select the mode of operation of the USART as shown in
Control and Status Register n C – UCSRnC” on page 167
USART operation. The MSPIM is enabled when both UMSELn bits are set to one. The
UDORDn, UCPHAn, and UCPOLn can be set in the same write operation where the MSPIM is
enabled.
• Bit 5:3 - Reserved Bits in MSPI mode
When in MSPI mode, these bits are reserved for future use. For compatibility with future devices,
these bits must be written to zero when UCSRnC is written.
• Bit 2 - UDORDn: Data Order
When set to one the LSB of the data word is transmitted first. When set to zero the MSB of the
data word is transmitted first. Refer to the Frame Formats section page 4 for details.
• Bit 1 - UCPHAn: Clock Phase
The UCPHAn bit setting determine if data is sampled on the leasing edge (first) or tailing (last)
edge of XCKn. Refer to the SPI Data Modes and Timing section page 4 for details.
• Bit 0 - UCPOLn: Clock Polarity
The UCPOLn bit sets the polarity of the XCKn clock. The combination of the UCPOLn and
UCPHAn bit settings determine the timing of the data transfer. Refer to the SPI Data Modes and
Timing section page 4 for details.
The function and bit description of the baud rate registers in MSPI mode is identical to normal
USART operation. See “USART Baud Rate Registers – UBRRLn and UBRRHn” on page 169.
The USART in MSPIM mode is fully compatible with the AVR SPI regarding:
Bit
Read/Write
Initial Value
• Master mode timing diagram.
• The UCPOLn bit functionality is identical to the SPI CPOL bit.
1
0
1
UMSELn0
0
7
UMSELn1
R/W
0
6
UMSELn0
R/W
0
Mode
Asynchronous USART
(Reserved)
Master SPI (MSPIM)
Synchronous USART
5
-
R
0
4
-
R
0
3
-
R
0
2
UDORDn
R/W
1
for full description of the normal
AT90USB82/162
1
UCPHAn
R/W
1
Table
18-3. See
0
UCPOLn
R/W
0
UCSRnC
“USART
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