AT90USB162 Atmel Corporation, AT90USB162 Datasheet - Page 134

• Manufacturer Part Number: AT90USB162
• Manufacturer: Atmel Corporation

Specifications of AT90USB162

• Flash (kbytes): 16 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 22
• Ext Interrupts: 21
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 5
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

15.10.5
15.10.6
15.10.7
15.10.8
15.10.9
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AT90USB82/162
Output Compare Register 1 A – OCR1AH and OCR1AL
Output Compare Register 1 B – OCR1BH and OCR1BL
Output Compare Register 1 C – OCR1CH and OCR1CL
Input Capture Register 1 – ICR1H and ICR1L
Timer/Counter1 Interrupt Mask Register – TIMSK1
The Output Compare Registers contain a 16-bit value that is continuously compared with the
counter value (TCNTn). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OCnx pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are
written simultaneously when the CPU writes to these registers, the access is performed using an
8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other
16-bit registers.
IThe Input Capture is updated with the counter (TCNTn) value each time an event occurs on the
ICPn pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture
can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit
registers.
• Bit 5 – ICIEn: Timer/Countern, Input Capture Interrupt Enable
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
See “Accessing 16-bit Registers” on page 109.
7
OCR1A[15:8]
OCR1A[7:0]
R/W
0
7
OCR1B[15:8]
OCR1B[7:0]
R/W
0
7
OCR1C[15:8]
OCR1C[7:0]
R/W
0
7
ICR1[15:8]
ICR1[7:0]
R/W
0
7
–
R
0
See “Accessing 16-bit Registers” on page 109.
6
–
R
0
6
R/W
0
6
R/W
0
6
R/W
0
6
R/W
0
R/W
5
R/W
0
5
R/W
0
5
R/W
0
5
R/W
0
5
ICIE1
0
4
–
R
0
4
R/W
0
4
R/W
0
4
R/W
0
4
R/W
0
3
OCIE1C
R/W
0
3
R/W
0
3
R/W
0
3
R/W
0
3
R/W
0
2
OCIE1B
R/W
0
2
R/W
0
2
R/W
0
2
R/W
0
2
R/W
0
1
R/W
0
1
R/W
0
1
R/W
0
1
R/W
0
1
OCIE1A
R/W
0
0
R/W
0
0
R/W
0
0
R/W
0
0
R/W
0
0
TOIE1
R/W
0
7707F–AVR–11/10
OCR1AH
OCR1AL
OCR1BH
OCR1BL
OCR1CH
OCR1CL
ICR1H
ICR1L
TIMSK1