AT90USB162 Atmel Corporation, AT90USB162 Datasheet - Page 18

• Manufacturer Part Number: AT90USB162
• Manufacturer: Atmel Corporation

Specifications of AT90USB162

• Flash (kbytes): 16 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 22
• Ext Interrupts: 21
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 5
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

5.2.1
5.3
18
EEPROM Data Memory
AT90USB82/162
Data Memory Access Times
The 32 general purpose working registers, 64 I/O registers, and the 512 bytes of internal data
SRAM in the AT90USB82/162 are all accessible through all these addressing modes. The Reg-
ister File is described in
Figure 5-2.
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
Figure 5-3.
The AT90USB82/162 contains 512 bytes of data EEPROM memory. It is organized as a sepa-
rate data space, in which single bytes can be read and written. The EEPROM has an endurance
of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is
described in the following, specifying the EEPROM Address Registers, the EEPROM Data Reg-
ister, and the EEPROM Control Register.
Address
clk
Data Memory Map
On-chip Data SRAM Access Cycles
Data
Data
WR
CPU
RD
“General Purpose Register File” on page
Compute Address
64 I/O
160 E xt I/O
D ata M emory
I nternal S RAM
32 R egisters
(512 x 8)
T1
Memory Access Instruction
R egisters
R eg .
Address valid
CPU
T2
$0000 - $001F
$0100
$2FF
$0020 - $005F
$0060 - $00FF
cycles as described in
Next Instruction
11.
T3
Figure
7707F–AVR–11/10
5-3.