AT90CAN64 Atmel Corporation, AT90CAN64 Datasheet - Page 64

• Manufacturer Part Number: AT90CAN64
• Manufacturer: Atmel Corporation

Specifications of AT90CAN64

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Can: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8.2
8.2.1
64
Moving Interrupts Between Application and Boot Space
AT90CAN32/64/128
MCU Control Register – MCUCR
The General Interrupt Control Register controls the placement of the Interrupt Vector table.
• Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash
memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot
Loader section of the Flash. The actual address of the start of the Boot Flash Section is deter-
mined by the BOOTSZ Fuses. Refer to the section
Programming” on page 321
special write procedure must be followed to change the IVSEL bit:
Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled
in the cycle IVCE is set, and they remain disabled until after the instruction following the write to
IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status
Register is unaffected by the automatic disabling.
Note:
Bit
Read/Write
Initial Value
1. Write the Interrupt Vector Change Enable (IVCE) bit to one.
2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is pro-
grammed, interrupts are disabled while executing from the Application section. If Interrupt Vectors
are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are dis-
abled while executing from the Boot Loader section. Refer to the section
Read-While-Write Self-Programming” on page 321
JTD
R/W
7
0
R
6
–
0
for details. To avoid unintentional changes of Interrupt Vector tables, a
R
5
–
0
PUD
R/W
4
0
R
3
–
0
“Boot Loader Support – Read-While-Write Self-
for details on Boot Lock bits.
R
2
–
0
IVSEL
R/W
1
0
IVCE
R/W
“Boot Loader Support –
0
0
MCUCR
7679H–CAN–08/08