AT90CAN64 Atmel Corporation, AT90CAN64 Datasheet - Page 308
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AT90CAN64
Manufacturer Part Number
AT90CAN64
Description
Manufacturer
Atmel Corporation
Specifications of AT90CAN64
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
53
Ext Interrupts
8
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
2
Can
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
8
Input Capture Channels
2
Pwm Channels
7
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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23.6.5
308
AT90CAN32/64/128
Scanning the Analog Comparator
Figure 23-7. Boundary-scan Cells for Oscillators and Clock Options
Table 23-5
XTAL1/XTAL2 connections as well as external Timer2 clock pin TOSC1 and 32kHz Timer2
Oscillator.
Table 23-5.
Notes:
The relevant Comparator signals regarding Boundary-scan are shown in
Boundary-scan cell from
described in
The Comparator need not be used for pure connectivity testing, since all analog inputs are
shared with a digital port pin as well.
Enable Signal
EXTCLKEN
OSCON
OSC32EN
TOSKON
1. Do not enable more than one clock source as clock at a time.
2. Scanning an Oscillator output gives unpredictable results as there is a frequency drift between
3. The main clock configuration is programmed by fuses. As a fuse is not changed run-time, the
From Digital Logic
the internal Oscillator and the JTAG TCK clock. If possible, scanning an external clock is
preferred.
main clock configuration is considered fixed for a given application. The user is advised to
scan the same clock option as to be used in the final system. The enable signals are sup-
ported in the scan chain because the system logic can disable clock options in sleep modes,
thereby disconnecting the Oscillator pins from the scan path if not provided.
summaries the scan registers for the external clock pin XTAL1, oscillators with
Table
Scan Signals for the Oscillators
Scanned Clock Line
EXTCLK (XTAL1)
OSCCK
OSC32CK
TOSCK
23-6.
Previous
From
Cell
ShiftDR
0
1
ClockDR
Figure 23-9
D
UpdateDR
Q
Next
Cell
To
D
G
is attached to each of these signals. The signals are
Q
Clock Option
External Main Clock
External Crystal
External Ceramic Resonator
Low Freq. External Crystal
32 kHz Timer2 Oscillator
EXTEST
0
1
(1)(2)(3)
XTAL1 / TOSC1
ENABLE
Oscillator
XTAL2 / TOSC2
OUTPUT
Previous
From
Cell
ShiftDR
0
1
ClockDR
Scanned Clock Line
when not Used
D
Figure
FF1
Q
Next
Cell
To
7679H–CAN–08/08
0
1
1
1
23-8. The
To System Logic