AT90CAN64 Atmel Corporation, AT90CAN64 Datasheet - Page 241

• Manufacturer Part Number: AT90CAN64
• Manufacturer: Atmel Corporation

Specifications of AT90CAN64

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Can: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

19.4
19.4.1
19.4.2
7679H–CAN–08/08
CAN Channel
Configuration
Bit Timing
The CAN channel can be in:
Figure 19-6. Listening Mode
FSM’s (Finite State Machine) of the CAN channel need to be synchronous to the time quantum.
So, the input clock for bit timing is the clock used into CAN channel FSM’s.
Field and segment abbreviations:
• Enabled mode
• Standby mode
• Listening mode
• BRP: Baud Rate Prescaler.
• TQ: Time Quantum (output of Baud Rate Prescaler).
• SYNS: SYNchronization Segment is 1 TQ long.
• PRS: PRopagation time Segment is programmable to be 1, 2, ..., 8 TQ long.
• PHS1: PHase Segment 1 is programmable to be 1, 2, ..., 8 TQ long.
• PHS2: PHase Segment 2 is programmable to be ≤ PHS1 and ≥ INFORMATION
• INFORMATION PROCESSING TIME is 2 TQ.
• SJW: (Re) Synchronization Jump Width is programmable between 1 and min(4, PHS1).
PROCESSING TIME.
– the CAN channel (internal TxCAN & RxCAN) is enabled,
– the input clock is enabled.
– the transmitter constantly provides a recessive level (on internal TxCAN) and the
– input clock is enabled,
– the registers and pages remain accessible.
– enables a hardware loop back, internal TxCAN on internal RxCAN
– provides a recessive level on TXCAN output pin
– does not disable RXCAN input pin
– freezes TEC and REC error counters
In this mode:
In standby mode:
This mode is transparent for the CAN channel:
receiver is disabled,
LISTEN
RxCAN
TxCAN
internal
internal
1
0
PD5
PD6
AT90CAN32/64/128
RXCAN
TXCAN
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