AT32UC3B1128 Atmel Corporation, AT32UC3B1128 Datasheet - Page 392

• Manufacturer Part Number: AT32UC3B1128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3B1128

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 60 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 28
• Ext Interrupts: 28
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32059L–AVR32–01/2012
The UDDMAnSTATUS.CHEN bit is 0 and the UDDMAnSTATUS.LDNXTCHDESCEN is set indi-
cating that the DMA channel is pending until the endpoint is ready (received OUT packet).
As soon as an OUT packet is stored inside the endpoint, the UDDMAnSTATUS.CHACTIVE bit
is set to one. Then after a few cycle latency, the new descriptor is loaded from the memory and
the UDDMAnSTATUS.DESCLDSTA is set.
At the end of this DMA (for instance when the channel byte length has reached 0), the
UDDMAnCONTROL.CHEN bit is cleared, and then the UDDMAnSTATUS.CHEN bit is also
cleared. If the UDDMAnCONTROL.LDNXTCH value is one, a new descriptor is loaded.
This sequence is repeated until a last linked descriptor is processed. The last descriptor is
detected according to row 2 as shown in
At the end of the last descriptor, the UDDMAnCONTROL.CHEN bit is cleared. As a conse-
quence, after a few cycles latency, the UDDMAnSTATUS.CHEN bit is also cleared.
• Set up the chain of linked list of descripor in memory. Each descriptor is composed of 3 items
• Program the UDDMAnNEXTDESC register.
• Program the UDDMAnCONTROL according to Row 3 as shown in
: channel next descriptor address, channel destination address and channel control. The last
descriptor should be programmed according to row 2 as shown in
Figure 22-6 on page
439.
Figure 22-6 on page
Figure 22-6 on page
439.
439.
392