AT32UC3B1128 Atmel Corporation, AT32UC3B1128 Datasheet - Page 196

• Manufacturer Part Number: AT32UC3B1128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3B1128

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 60 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 28
• Ext Interrupts: 28
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

18.5
Table 18-1.
18.6
18.6.1
18.6.2
18.6.3
18.7
18.7.1
18.7.2
32059L–AVR32–01/2012
Pin Name
MISO
MOSI
SPCK
NPCS1-NPCS3
NPCS0/NSS
Signal Description
Product Dependencies
Functional Description
I/O Lines
Power Management
Interrupt
Modes of Operation
Data Transfer
The pins used for interfacing the compliant external devices may be multiplexed with GPIO lines.
The programmer must first program the GPIO controller to assign the SPI pins to their peripheral
functions.To use the local loopback function the SPI pins must be controlled by the SPI.
The SPI may be clocked through the Power Manager, Before using the SPI, the programmer
must ensure that the SPI clock is enabled in the Power Manager.
In the SPI description, CLK_SPI is the clock of the peripheral bus to which the SPI is connected.
The SPI interface has an interrupt line connected to the Interrupt Controller (INTC). Handling the
SPI interrupt requires programming the INTC before configuring the SPI.
The SPI operates in Master Mode or in Slave Mode.
Operation in Master Mode is programmed by writing at 1 the MSTR bit in the Mode Register.
The pins NPCS0 to NPCS3 are all configured as outputs, the SPCK pin is driven, the MISO line
is wired on the receiver input and the MOSI line driven as an output by the transmitter.
If the MSTR bit is written at 0, the SPI operates in Slave Mode. The MISO line is driven by the
transmitter output, the MOSI line is wired on the receiver input, the SPCK pin is driven by the
transmitter to synchronize the receiver. The NPCS0 pin becomes an input, and is used as a
Slave Select signal (NSS). The pins NPCS1 to NPCS3 are not driven and can be used for other
purposes.
The data transfers are identically programmable for both modes of operations. The baud rate
generator is activated only in Master Mode.
Four combinations of polarity and phase are available for data transfers. The clock polarity is
programmed with the CPOL bit in the Chip Select Register. The clock phase is programmed with
Pin Description
Master In Slave Out
Master Out Slave In
Serial Clock
Peripheral Chip Selects
Peripheral Chip Select/Slave Select
Output
Output
Output
Master
Input
Output
Type
Slave
Output
Input
Input
Unused
Input
196