AT32UC3B1128 Atmel Corporation, AT32UC3B1128 Datasheet - Page 207

• Manufacturer Part Number: AT32UC3B1128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3B1128

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 60 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 28
• Ext Interrupts: 28
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

18.8.1
Name:
Access Type:
Offset:
Reset Value:
• LASTXFER: Last Transfer
• SWRST: SPI Software Reset
• SPIDIS: SPI Disable
• SPIEN: SPI Enable
32059L–AVR32–01/2012
SWRST
31
23
15
–
–
–
7
0: No effect.
1: The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this allows
to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has
completed.
0: No effect.
1: Reset the SPI. A software-triggered hardware reset of the SPI interface is performed.
The SPI is in slave mode after software reset.
Peripheral DMA Controller
0: No effect.
1: Disables the SPI.
As soon as SPIDIS is set, SPI finishes its tranfer.
All pins are set in input mode and no data is received or transmitted.
If a transfer is in progress, the transfer is finished before the SPI is disabled.
If both SPIEN and SPIDIS are equal to one when the control register is written, the SPI is disabled.
0: No effect.
1: Enables the SPI to transfer and receive data.
Control Register
30
22
14
CR
Write-only
0x00
0x00000000
–
–
–
6
–
channels are not affected by software reset.
29
21
13
–
–
–
5
–
28
20
12
–
–
–
4
–
27
19
11
–
–
–
3
–
26
18
10
–
–
–
–
2
SPIDIS
25
17
–
–
–
9
1
LASTXFER
SPIEN
24
16
–
8
0
-
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