AT32UC3A4128 Atmel Corporation, AT32UC3A4128 Datasheet - Page 84
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AT32UC3A4128
Manufacturer Part Number
AT32UC3A4128
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A4128
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
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Manufacturer
Quantity
Price
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Part Number:
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Manufacturer:
ATMEL
Quantity:
2 620
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Part Number:
AT32UC3A4128S-CIUT
Manufacturer:
ATMEL
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Part Number:
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20 000
Company:
Part Number:
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12 914
Company:
Part Number:
AT32UC3A4128SC101
Manufacturer:
STM
Quantity:
6 278
Company:
Part Number:
AT32UC3A4128SC1UT
Manufacturer:
ATMEL
Quantity:
6 055
8.18
8.19
8.19.1
32002F–03/2010
Read-modify-write instructions
Code example
Assumptions
Table 8-14.
This group contains instructions that perform atomical bit-operations on memory addresses.
These instructions require multiple cycles inside the memory controller, but these can be per-
formed in parallel with subsequent instructions if the following instructions are not memory
access instructions.
A RMW instruction performed on an address in the IRAM section executes in a single cycle if the
IRAM write buffer is empty. If the write buffer is not empty, two cycles are required. The pro-
grammer can make sure the buffer is empty by ensuring that the instruction immediately before
the RMW instruction is not a store or another RMW instruction.
If the RMW instruction is performed on an address in the HSB section, four cycles are needed
for the RMW instruction to be executed. Therefore, if another instruction attempts to access
memory within one of the three following clock cycles, up to three stall cycles will be inserted. If
a memory access instruction is scheduled less than 3 cycles after the RMW to HSB instruction,
3-n stall cycles are inserted. Here n is the number of cycles used by instructions between the
RMW instruction and the first memory access instruction. RMW operations to the HSB section
will take additional cycles if the HSB inserts wait states.
When using RMW instructions, try to schedule code so that stall cycles are avoided.
Table 8-15.
In the example code given in this chapter, the following assumptions are made:
pref
sleep
sync
Mnemonics
memc
mems
memt
• r0 points to an address in the IRAM space. IRAM is an alias for r0.
• r1 points to an address in the HSB or BOOT space. HSB is an alias for r1.
• All memories and buses have 0 wait state access.
• The CPU is in a priviliged mode, so that no privilege violations occur
System control instructions
Read-modify-write instructions to IRAM section
E
E
E
E
E
E
Rp[disp]
Op8
Op8
Operands
imm, bp
imm, bp
imm, bp
Description
Clear bit in memory.
Set bit in memory.
Toggle bit in memory.
Prefetch cache line.
Enter SLEEP mode.
Flush write buffer.
Execution
cycles IRAM
1/2
1/2
1/2
Execution
cycles HSB
4
4
4
AVR32
1
1
1
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