AT32UC3A4128 Atmel Corporation, AT32UC3A4128 Datasheet - Page 106
![no-image](/images/manufacturer_photos/0/0/79/atmel_corporation_sml.jpg)
AT32UC3A4128
Manufacturer Part Number
AT32UC3A4128
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A4128
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A4128S-C1UR
Manufacturer:
ATMEL
Quantity:
2 620
Company:
Part Number:
AT32UC3A4128S-CIUT
Manufacturer:
ATMEL
Quantity:
350
Part Number:
AT32UC3A4128S-CIUT
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
AT32UC3A4128S-U
Manufacturer:
ATMEL
Quantity:
12 914
Company:
Part Number:
AT32UC3A4128SC101
Manufacturer:
STM
Quantity:
6 278
Company:
Part Number:
AT32UC3A4128SC1UT
Manufacturer:
ATMEL
Quantity:
6 055
9.2.14.8
32002F–03/2010
Development Status (DS) register
Table 9-11.
This register is used to examine the debug state of the CPU and the cause for entering Debug
Mode. Note that multiple sources may trigger Debug Mode simultaneously, causing more than
one bit to be set. The register is read-only. All bits are dynamic and do not require clearing.
R/W
R/W
R/W
R/W
Bit Number
7:5
4:3
2:0
Development Control Register
Field Name
OVC
EIC
TM
Init. Val.
0
0
0
Description
OVC[2:0] - Overrun Control
OVC controls the action taken if Branch, Data, or
Ownership trace messages are generated while
the Transmit Queue is full. Settings 111 though
100 are reserved.
000 = Generate overrun messages
001 = Delay CPU to avoid BTM and Ownership
Trace overruns
010 = Delay CPU to avoid DTM and Ownership
Trace overruns
011 = Delay CPU to avoid BTM, DTM, and
Ownership Trace overruns
111-100 = Reserved
EIC[1:0] - EVTI Control
The EIC bits control the action performed when
the EVTI pin on the Nexus debug port receives a
high-to-low transition. If trace is enabled, EVTI can
be configured to cause a trace synchronization
message. If Debug Mode is enabled, EVTI can be
configured to cause a breakpoint.
00 = EVTI for program and data trace
synchronization
01 = EVTI for breakpoint generation
10 = No operation
11 = Reserved
TM[2:0] - Trace Mode
The TM bits select which trace modes are
enabled.
000 = No Trace
XX1 = OTM Enabled
X1X = DTM Enabled
1XX = BTM Enabled
If Data or Branch tracing is triggered or stopped by
a watchpoint , the DTM and BTM bits are updated
accordingly.
AVR32
106