AT32UC3A4128 Atmel Corporation, AT32UC3A4128 Datasheet - Page 25
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AT32UC3A4128
Manufacturer Part Number
AT32UC3A4128
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A4128
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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3.8.3
32002F–03/2010
Masking interrupt requests in peripheral modules
This can usually be ensured by scheduling the code sequence disasserting the interrupt request
in such a way that one can be certain that the interrupt request has actually been disasserted
before the rete instruction is executed.
Code 3-1.
The mechanisms and timing required for disasserting an interrupt request from a module is spe-
cific to different modules. Usually, the request is disasserted within a few clock cycles after the
load or store instruction has been received by the module. In this case, a simple way of making
sure that the request has actually been disasserted is to use a data memory barrier
ory barriers” on page
been disasserted. At this point, the rete instruction can safely be executed.
Code 3-2.
The programmer should consult the data sheets for the different peripheral modules to check if
special timings or concerns related to disasserting of interrupt requests apply to the specific
module.
Handling an interrupt request involves several operations like pushing of registers to stack and
takes several clock cycles. The required operations are controlled by sequencing logic in hard-
ware. This sequencing hardware does not permit that an asserted interrupt request is
disasserted while it is in the process of handling this interrupt request.
Hardware makes sure that manipulation of the GM and IxM bits in SREG can be performed
safely at all times using the mtsr, csrf and ssrf instructions. The programmer does not need to
take any special concerns when issuing one of these instructions.
All hardware connected to the CPU is implemented in such a way that once an interrupt request
is asserted by the hardware, it can only be disasserted by explicit actions by the programmer.
// Using scheduling of instructions in the IRQ handler to make sure that the
// request has been disasserted before returning from the handler.
// Assume that the IRQ is cleared by reading PERIPH_INTCAUSE, r0 points to
// this register.
irq_handler:
// Using data memory barriers in the IRQ handler to make sure that the
// request has been disasserted before returning from the handler
// Assume that the IRQ is cleared by writing a bitmask to PERIPH_INTCLEAR.
// r0 points to this register, r1 contains the correct bitmask.
irq_handler:
<some instructions>
ld.w r12, r0[0] // Clear the IRQ
<some other instructions, enough to make sure that the IRQ is cleared>
rete
<some instructions>
st.w r0[0], r1
ld.w r12, r0[0] // data memory barrier
rete
Clearing IRQs using code scheduling
Clearing IRQs using data memory barriers
64). The DMB will block the CPU pipeline until the interrupt request has
AVR32
(“Data mem-
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