AT32UC3A4128 Atmel Corporation, AT32UC3A4128 Datasheet - Page 102
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AT32UC3A4128
Manufacturer Part Number
AT32UC3A4128
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A4128
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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9.2.14.4
9.2.14.5
32002F–03/2010
Debug Communication Emulator Register (DCEMU)
Debug Communication Status Register (DCSR)
Communication Status Register. The emulator should poll the status register and read DCCPU if
the dirty bit is set.
Table 9-7.
When the emulator writes to this register, a dirty bit is set in the Debug Communication Status
register. The CPU can poll this bit to see if DCEMU contains unread data..
Table 9-8.
To avoid overruns the CPU must poll this register before writing a new value to DCCPU. Note
that the bits in this register are not automatically cleared in OCD mode. This allows a debugger
to update views and observe the system without accidentally modifying the DCSR register.
The OCD system can produce interrupts when the DCEMU register has been updated and when
the DCCPU register is read. The CPURI and EMUDI flags are set on the interrupt events, but
are cleared by software by writing the DCSR register. To enable the interrupts the corresponding
bits in the DCCR register has to be set and the Interrpt controller has to be programmed.
Table 9-9.
R/W
R/W
R/W
R/W
R/W
R
R/W
Bit Number
31:0
Bit Number
31:0
Bit Number
31:4
1
Debug Communication CPU Register
Debug Communication Emulator Register
Debug Communication Status Register
Field Name
DATA
Field Name
DATA
Field Name
Reserved
EMUDI
Init. Val.
0x0000_
0000
Init. Val.
0x0000_
0000
Init. Val.
0x0000_
0000
0
Description
Data Value
Data written by CPU
Description
Data Value
Data written by Emulator
Description
Reserved
These bits are reserved, and will always read as 0
Emulator Data Dirty Interrupt flag
0 = DCEMU has not been written to since the
clearing of this bit.
1 = DCEMU contains a new data value.
This bit is cleared by writing this bit to 0.
AVR32
102