AT32UC3A4128 Atmel Corporation, AT32UC3A4128 Datasheet - Page 29
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AT32UC3A4128
Manufacturer Part Number
AT32UC3A4128
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A4128
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
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Manufacturer:
ATMEL
Quantity:
2 620
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Part Number:
AT32UC3A4128S-CIUT
Manufacturer:
ATMEL
Quantity:
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Part Number:
AT32UC3A4128S-CIUT
Manufacturer:
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20 000
Company:
Part Number:
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Manufacturer:
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12 914
Company:
Part Number:
AT32UC3A4128SC101
Manufacturer:
STM
Quantity:
6 278
Company:
Part Number:
AT32UC3A4128SC1UT
Manufacturer:
ATMEL
Quantity:
6 055
3.9.1.2
3.9.1.3
3.9.1.4
3.9.1.5
32002F–03/2010
Unrecoverable Exception
TLB Multiple Hit Exception
OCD Stop CPU Exception
Bus Error Exception on Data Access
All other system registers are reset to their reset value, which may or may not be defined. Refer
to the Programming Model chapter for details.
The OCD Stop CPU exception is generated when the OCD Stop CPU input line to the CPU is
asserted. The OCD Stop CPU exception can not be masked by any bit. This exception is identi-
cal to a non-maskable, high priority breakpoint. Any subsequent operation is controlled by the
OCD hardware. The OCD hardware will take control over the CPU and start to feed instructions
directly into the pipeline.
The Unrecoverable Exception is generated when an exception request is issued when the
Exception Mask (EM) bit in the status register is asserted. The Unrecoverable Exception can not
be masked by any bit. The Unrecoverable Exception is generated when a condition has
occurred that the hardware cannot handle. The system will in most cases have to be restarted if
this condition occurs.
The TLB Multiple Hit Exception is generated when an access hits in multiple MPU regions. This
is usually caused by programming error. Used only if an MPU is present.
The Bus Error on Data Access exception is generated when the data bus detects an error condi-
tion. This exception is caused by events unrelated to the instruction stream, or by data written to
the cache write-buffers many cycles ago. Therefore, execution can not be resumed in a safe
way after this exception. The return address placed on stack is unrelated to the operation that
PC = 0x8000_0000;
RSR_DBG = SR;
RAR_DBG = PC;
SR[M2:M0] = B’110;
SR[D] = 1;
SR[DM] = 1;
SR[EM] = 1;
SR[GM] = 1;
*(--SP
*(--SP
SR[M2:M0] = B’110;
SR[EM] = 1;
SR[GM] = 1;
PC = EVBA | 0x00;
*(--SP
*(--SP
SR[M2:M0] = B’110;
SR[EM] = 1;
SR[GM] = 1;
PC = EVBA | 0x04;
SYS
SYS
SYS
SYS
) = PC of offending instruction;
) = SR;
) = PC of offending instruction;
) = SR;
AVR32
29