AT32UC3A4128 Atmel Corporation, AT32UC3A4128 Datasheet - Page 37
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AT32UC3A4128
Manufacturer Part Number
AT32UC3A4128
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A4128
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Company
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Manufacturer
Quantity
Price
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Company:
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Manufacturer:
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6 278
Company:
Part Number:
AT32UC3A4128SC1UT
Manufacturer:
ATMEL
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6 055
3.9.1.26
3.9.1.27
3.9.1.28
3.10
32002F–03/2010
Interrupt latencies
Floating-point Exception
Coprocessor Absent Exception
Supervisor call
Unused in AVR32UC.
The Coprocessor Absent exception is generated when a nonexisting coprocessor is addressed
by a coprocessor instruction. Used only if one or more coprocessors are present. Executing
coprocessor instructions in systems with no coprocessors results in an Unimplemented Instruc-
tion exception instead.
Supervisor calls are signalled by the application code executing a supervisor call (scall) instruc-
tion. The scall instruction behaves differently depending on which context it is called from. This
allows scall to be called from other contexts than Application.
When the exception routine is finished, execution continues at the instruction following scall. The
rets instruction is used to return from supervisor calls.
The following features in AVR32UC ensure low and deterministic interrupt latency:
• Four different interrupt levels and an NMI ensures that the user can efficiently prioritize the
• Long-running instructions such as ldm, stm, pushm, popm, divs and divu will be aborted if an
• Interrupts are autovectored, allowing the CPU to jump directly to the interrupt handler.
• When an interrupt of level m is received, the CPU will start stacking register file registers,
interrupt sources.
interrupt request is received. The slowest instruction that can not be aborted by a pending
interrupt has a worst case issue latency of 5 cycles. This implies that an interrupt request will
need to wait at most 5 cycles for an instruction to complete. The fastest instructions need
only a single cycle to complete.
return address and status register. After this stacking is performed, the CPU will jump to the
autovector address of the interrupt of level m. If an interrupt of level n, where n > m, is
received during this stacking, the CPU will jump to the autovector address of the interrupt of
level n, NOT the autovector address of the original interrupt.
*(--SP
*(--SP
SR[M2:M0] = B’110;
SR[EM] = 1;
SR[GM] = 1;
PC = EVBA | 0x30;
If ( SR[M2:M0] == {B’000 or B’001} )
else
*(--SP
*(--SP
PC ← EVBA | 0x100;
SR[M2:M0] ← B’001;
LR ← PC + 2;
PC ← EVBA | 0x100;
SYS
SYS
SYS
SYS
) = PC;
) = SR;
) = PC;
) = SR;
AVR32
37