AT32UC3A1256AU Atmel Corporation, AT32UC3A1256AU Datasheet - Page 503
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AT32UC3A1256AU
Manufacturer Part Number
AT32UC3A1256AU
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(98 pages)
2.AT32UC3A0128.pdf
(826 pages)
3.AT32UC3A0128.pdf
(377 pages)
4.AT32UC3A0128.pdf
(33 pages)
5.AT32UC3A0128.pdf
(159 pages)
6.AT32UC3A0128AU.pdf
(2 pages)
Specifications of AT32UC3A1256AU
Flash (kbytes)
256 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
69
Ext Interrupts
69
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
1
Uart
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A0128 PDF datasheet #4
- AT32UC3A0128 PDF datasheet #5
- AT32UC3A0128AU PDF datasheet #6
- Current page: 503 of 826
- Download datasheet (11Mb)
32058K AVR32-01/12
30.7
30.7.1
30.7.1.1
30.7.1.2
Figure 30-5. General States
Functional Description
USB General Operation
Introduction
Power-On and Reset
After a hardware reset, the USB controller is disabled. When enabled, the USB controller runs
either in device mode or in host mode according to the ID detection.
If the USB_ID pin is not connected to ground, the ID bit is set by hardware (the internal pull-up
resistor of the USB_ID pin must be enabled by the GPIO controller) and device mode is
engaged.
The ID bit is cleared by hardware when a low level has been detected on the USB_ID pin. Host
mode is then engaged.
Figure 30-5
After a hardware reset, the USB controller is in the Reset state. In this state:
After setting USBE, the USB controller enters the Device or the Host mode (according to the ID
detection) in idle state.
The USB controller can be disabled at any time by clearing USBE. In fact, clearing USBE acts
as a hardware reset, except that the OTGPADE, VBUSPO, FRZCLK, UIDE, UIMOD and LS bits
are not reset.
•the macro is disabled (USBE = 0);
•the macro clock is stopped in order to minimize power consumption (FRZCLK = 1);
•the pad is in suspend mode;
•the internal states and registers of the device and host modes are reset;
•the DPRAM is not cleared and is accessible;
•the ID and VBUS read-only bits reflect the states of the USB_ID and VBUS input pins;
•the OTGPADE, VBUSPO, FRZCLK, USBE, UIDE, UIMOD and LS bits can be written by
software, so that the user can program pads and speed before enabling the macro, but their
value is only taken into account once the macro is enabled and unfrozen.
describes the USB controller main states.
Clock stopped:
FRZCLK = 1
Device
Macro off:
USBE = 0
USBE = 1
ID = 1
USBE = 0
Reset
USBE = 1
ID = 0
USBE = 0
USBE = 0
Host
RESET
HW
state>
<any
other
AT32UC3A
503
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