AT32UC3A1256AU Atmel Corporation, AT32UC3A1256AU Datasheet - Page 462

• Manufacturer Part Number: AT32UC3A1256AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A1256AU

• Flash (kbytes): 256 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 69
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32058K AVR32-01/12
29.7.5
Register Name:
Access Type:
This register points to the entry in the receive buffer queue (descriptor list) currently being used. It is written with the start
location of the receive buffer descriptor list. The lower order bits increment as buffers are used up and wrap to their original
values after either 1024 buffers or when the wrap bit of the entry is set.
Reading this register returns the location of the descriptor currently being accessed. This value increments as buffers are
used. Software should not use this register for determining where to remove received frames from the queue as it con-
stantly changes as new frames are received. Software should instead work its way through the buffer descriptor queue
checking the used bits.
Receive buffer writes also comprise bursts of two words and, as with transmit buffer reads, it is recommended that bit 2 is
always written with zero to prevent a burst crossing a 1K boundary, in violation of the System Bus specification.
• ADDR:
Written with the address of the start of the receive queue, reads as a pointer to the current buffer being used.
31
23
15
7
Receive buffer queue pointer address
Receive Buffer Queue Pointer Register
30
22
14
RBQP
6
Read/Write
29
21
13
5
ADDR
28
20
12
4
ADDR
ADDR
ADDR
27
19
11
3
26
18
10
2
25
17
9
1
–
AT32UC3A
24
16
8
0
–
462