SC28L202A1DGG,118 NXP Semiconductors, SC28L202A1DGG,118 Datasheet - Page 6
SC28L202A1DGG,118
Manufacturer Part Number
SC28L202A1DGG,118
Description
IC UART DUAL W/FIFO 56-TSSOP
Manufacturer
NXP Semiconductors
Series
IMPACTr
Datasheet
1.SC28L202A1DGG118.pdf
(77 pages)
Specifications of SC28L202A1DGG,118
Features
False-start Bit Detection
Number Of Channels
2, DUART
Fifo's
256 Byte
Voltage - Supply
3.3V, 5V
With Parallel Port
Yes
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
56-TFSOP (0.240", 6.10mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935276109118
SC28L202A1DGG-T
SC28L202A1DGG-T
SC28L202A1DGG-T
SC28L202A1DGG-T
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SC28L202A1DGG,118
Manufacturer:
EPCOS
Quantity:
12 000
Philips Semiconductors
LIST OF FIGURES
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm (SOT364-1)
LIST OF TABLES
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
2005 Nov 01
Dual universal asynchronous receiver/transmitter
(DUART)
80xxx TSSOP56
68xxx TSSOP56
Active area in 68K mode.
Reset Timing (80XXX mode)
Reset Timing (68XXX mode)
Bus Timing (80XXX mode)
Bus Timing (Read Cycle) (68XXX mode)
Bus Timing (Write Cycle) (68XXX mode)
Interrupt Cycle Timing (68XXX mode)
Port Timing
Interrupt Timing (80xxx mode)
Clock Timing
Transmitter External Clocks
Receiver External Clock
Transmitter Timing
Receiver Timing
Wake-Up Mode
Test Conditions on Outputs
Interrupt Values
SC28L202 REGISTER BIT DESCRIPTIONS
Receiver FIFO Interrupt Fill Level MR0(3)=0
Receiver FIFO Interrupt Fill Level MR0(3)=1
Transmitter FIFO Interrupt Fill Level MR0(3)=0
Transmitter FIFO Interrupt Fill Level MR0(3)=0
SC28L92 Register Addressing READ (RDN = 0) WRITE (WRN = 0)
Baud Rate Generator Characteristics
Receiver FIFO Interrupt Fill Level MR0(3)=0
Receiver FIFO Interrupt Fill Level MR0(3)=1
Transmitter FIFO Interrupt Fill Level MR0(3)=0
Transmitter FIFO Interrupt Fill Level MR0(3)=1
Baud Rate (Base on a 14.7456 MHz crystal clock)
ACR 6:4 Field Definition
Interrupt Values
SC28L202 REGISTER BIT DESCRIPTIONS
Receiver FIFO Interrupt Fill Level MR0(3)=0
Receiver FIFO Interrupt Fill Level MR0(3)=1
Transmitter FIFO Interrupt Fill Level MR0(3)=0
Transmitter FIFO Interrupt Fill Level MR0(3)=0
SC28L92 Register Addressing READ (RDN = 0) WRITE (WRN = 0)
Baud Rate Generator Characteristics
Receiver FIFO Interrupt Fill Level MR0[3] = 0
Receiver FIFO Interrupt Fill Level MR0[3] = 1
Transmitter FIFO Interrupt Fill Level MR0[3] = 0
Transmitter FIFO Interrupt Fill Level MR0[3] = 1
Baud Rate (Base on a 14.7456 MHz crystal clock)
ACR 6:4 Field Definition
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v
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SC28L202
Product data sheet
61
62
62
62
63
63
64
64
65
65
66
66
66
67
67
68
69
14
19
21
21
21
21
39
40
41
41
41
41
44
46
14
18
20
20
20
20
39
40
41
41
41
41
44
46
2
2
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