SC28L202A1DGG,118 NXP Semiconductors, SC28L202A1DGG,118 Datasheet - Page 20

• Manufacturer Part Number: SC28L202A1DGG,118
• Description: IC UART DUAL W/FIFO 56-TSSOP
• Manufacturer: NXP Semiconductors
• Series: IMPACTr

Specifications of SC28L202A1DGG,118

• Features: False-start Bit Detection
• Number Of Channels: 2, DUART
• Fifo's: 256 Byte
• Voltage - Supply: 3.3V, 5V
• With Parallel Port: Yes
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 56-TFSOP (0.240", 6.10mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935276109118; SC28L202A1DGG-T; SC28L202A1DGG-T

Philips Semiconductors
Table 1. Interrupt Values
Interrupt Arbitration and IRQN generation
Interrupt arbitration is the process used to determine that an
interrupt request should be presented to the host. The arbitration is
carried out between the ‘Interrupt Threshold’ and the ‘sources’
whose interrupt bidding is enabled by the IMR. The interrupt
threshold is part of the ICR (Interrupt Control Register) and is a
value programmed by the user. The ‘sources’ present a value to the
interrupt arbiter. That value is derived from four fields: the channel
number, type of interrupts source, FIFO fill level, and a
programmable value. The interrupt request (IRQN) will be asserted
only when one or more of these values exceeds the threshold value
in the interrupt control register will.
Following assertion of the IRQN the host will either assert IACKN
(Interrupt Acknowledge) or will use the command to ‘Update the
CIR’. At the time either action is taken the CIR will capture the value
of the source that is prevailing in the arbitration process. (Call this
value the winning bid).
The Sclk drives the arbitration process. It evaluates the 12 bits of
the arbitration bus at
every two Sclk cycles. New arbitration values presented to the
arbitration block during an arbitration cycle will be evaluated in the
next arbitration cycle.
For sources other than receiver and transmitters the user may set
the high order bits of an interrupt source’s bid value, thus tailoring
the relative priority of the interrupt sources. The fill level of their
respective FIFOs controls the priority of the receivers and
transmitters. The more filled spaces in the RxFIFO the higher the bid
value; the more empty spaces in the TxFIFO the higher its priority.
Channels whose programmable high order bits are set will be given
interrupt priority higher than those with zeros in their high order bits,
thus allowing increased flexibility. The transmitter and receiver bid
values contain the character counts of the associated FIFOs as high
order bits in the bid value. Thus, as a receiver’s RxFIFO fills, it bids
with a progressively higher priority for interrupt service. Similarly, as
empty space in a transmitter’s TxFIFO increases, its interrupt
arbitration priority increases.
The programmable fields allow the software to adjust the authority or
value of the bid for those devices not having a FIFO.
For example: The break condition is sometimes used to signal a
starting point in a continuous stream of data. A Continuous running
2005 Nov 01
Type
Receiver w/o error
Receiver w/ error
Receiver Watch-dog
Transmitter
Change of Break
Rx Loop Back Error
Change of State
Xon/Xoff
Counter timer
Address Recognition
No interrupt
Threshold
Dual UART
the Sclk rate developing a value for the CIR
Bit 11:4
RxFIFO filled Byte Count
RxFIFO filled Byte Count
RxFIFO filled Byte Count
TxFIFO empty Byte Count
Programmed Field
Programmed Field
Programmed Field
Programmed Field
Programmed Field
Programmed Field
0
Bits 7:0 of Interrupt Control Register (ICR)
14
weather report or stock market ‘ticker-tape’ report needs breaks in
the data so that a receiver knows where the data starts. Once start
of the break is detected it is important to reset the ‘change of break’
interrupt so that this bit can signal the condition of the break ending.
This is signaled by the ‘L202 the setting another change of break
event in the ISR. Since it is assumed the data will be starting very
soon after the end of break it is important to give the change of
break condition a high priority. This may be accomplished by setting
the arbitration value for the ‘change of break’ to a high value. The
value in the ‘change of break programmable field’ in Table 1 would
be 0x7F.
IACKN Cycle, Update CIR
When the host CPU responds to the interrupt, it will usually assert
the IACKN signal low. This will cause the DUART to generate an
IACKN cycle in which the condition of the interrupting device is
determined. When IACKN asserts, the last valid interrupt number is
captured in the CIR. The value captured presents most of the
important details of the highest priority interrupt at the moment the
IACKN (or the ‘Update CIR’ command) was asserted.
The Dual UART will respond to the IACKN cycle with an interrupt
vector. The interrupt vector may be a fixed value, the content of the
Interrupt Vector Register, or when ‘Interrupt Vector Modification’ is
enabled via ICR, it may contain codes for the interrupt type and/or
interrupting channel. This allows the interrupt vector to steer the
interrupt service directly to the proper service routine. The interrupt
value captured in the CIR remains until another IACKN cycle occurs
or until an ‘Update CIR’ command is given to the DUART. The
interrupting channel and interrupt type fields of the CIR set the
current ‘interrupt context’ of the DUART. The channel component of
the interrupt context allows the use of Global Interrupt Information
registers that appear at fixed positions in the register address map.
For example, a read of the Global RxFIFO will read the channel B
RxFIFO if the CIR interrupt context is channel B receiver. At another
time read of the GRxFIFO may read the channel A RxFIFO (CIR
holds a channel A receiver interrupt) and so on. Global registers
exist to facilitate qualifying the interrupt parameters and for writing to
and reading from FIFOs without explicitly addressing them.
The CIR will load with x’00 if IACKN or Update CIR is asserted when
the arbitration circuit is NOT asserting an interrupt. In this condition
there is no arbitration value that exceeds the threshold value. When
Interrupt vector modification is active in this situation the interrupt
vector bits associated with the CIR will all be zero.
1
1
0
0
1
1
0
0
Bit 3
0
1
1
0
1
1
1
1
0
0
0
0
Bit 2
0
0
0
1
1
1
1
1
0
1
0
0
Bit 1
1
1
0
0
0
1
0
1
0
1
0
0
Bit 0
Channel No.
Channel No.
Channel No.
Channel No.
Channel No.
Channel No.
Port 0 or 1
Channel No.
Counter 0 or 1
Channel No.
0
SC28L202
Product data sheet