SC28L202A1DGG,118 NXP Semiconductors, SC28L202A1DGG,118 Datasheet - Page 26

• Manufacturer Part Number: SC28L202A1DGG,118
• Description: IC UART DUAL W/FIFO 56-TSSOP
• Manufacturer: NXP Semiconductors
• Series: IMPACTr

Specifications of SC28L202A1DGG,118

• Features: False-start Bit Detection
• Number Of Channels: 2, DUART
• Fifo's: 256 Byte
• Voltage - Supply: 3.3V, 5V
• With Parallel Port: Yes
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 56-TFSOP (0.240", 6.10mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935276109118; SC28L202A1DGG-T; SC28L202A1DGG-T

Philips Semiconductors
UART Registers
These registers are generally concerned with formatting,
transmitting and receiving data.
The user must exercise caution when changing the mode of running
receivers, transmitters, PBRG or counter/timers. The selected mode
will be activated immediately upon selection, even if this occurs
during the reception or transmission of a character. It is also
possible to disrupt internal controllers by changing modes at critical
MR0 – Mode Register 0, A and B
MR0 can be accessed directly at H’20’ and H’28’ in the Extended section of the address map, or by means of the ‘MR Pointers’ at the 0x00 and
0x08 address pointers used by legacy code.
*This bit control is duplicated at WCXER[7:6], the Watch Dog, Character, Address and X Enable Register.
MR0[7] Fixed length Watchdog Timer
This bit controls the receiver watchdog timer. 0 = disable, 1 =
enable. When enabled, the watch dog timer will generate a receiver
interrupt if the receiver FIFO has not been accessed within 64 bit
times of the receiver 1X clock. This is used to alert the control
processor that data is in the RxFIFO that has not been read. This
situation may occur when the byte count of the last part of a
message is not large enough to generate an interrupt.
MR0[6] – Bit 2 of receiver FIFO interrupt level. This bit along with Bit
6 of MR1 sets the fill level of the 8 byte FIFO that generates the
receiver interrupt.
MR0[6] and MR1[6] Note that this control is split between MR0 and
MR1. This is for backward compatibility to the SC2692 and
SCN2681.
Table 3. Receiver FIFO Interrupt Fill Level
Table 4. Receiver FIFO Interrupt Fill Level
For the receiver these bits control the number of FIFO positions
filled when the receiver will attempt to interrupt. After the reset the
receiver FIFO is empty. The default setting of these bits cause the
receiver to attempt to interrupt when it has one or more bytes in it.
2005 Nov 01
MR0[6] MR1[6]
00
01
10
11
MR0[6] MR1[6]
00
01
10
11
Dual UART
MR0 A, MR0
B, and
MR0 B[3:0]
are reserved
MR0(3)=0
MR0(3)=1
Interrupt Condition
1 or more bytes in FIFO (RxRDY)
128 or more bytes in FIFO
192 or more bytes in FIFO
256 bytes in FIFO (Rx FULL)
Interrupt Condition
1 or more bytes in FIFO (RxRDY)
3 or more bytes in FIFO
6 or more bytes in FIFO
8 bytes in FIFO (Rx FULL)
Bit 7
Rx Watchdog
*
0 = Disable
1 = Enable
BIT 6
RxINT BIT 2
See Tables in
MR0
description
BIT (5:4)
TxINT (1:0)
See Table 13
20
times, thus rendering later transmission or reception faulty or
impossible.
An exception to this policy is switching from auto-echo or remote
loop back modes to normal mode. If the deselecting occurs just after
the receiver has sampled the stop bit (in most cases indicated by
the assertion of the channel’s RxRDY bit) and the transmitter is
enabled, the transmitter will remain in auto-echo mode until the end
of the transmission of the stop bit.
MR0[5:4] – Tx interrupt fill level.
Table 5. Transmitter FIFO Interrupt Fill Level
Table 6. Transmitter FIFO Interrupt Fill Level
For the transmitter these bits control the number of FIFO positions
empty when the receiver will attempt to interrupt. After the reset the
transmit FIFO has 8 bytes empty. It will then attempt to interrupt as
soon as the transmitter is enabled. The default setting of the MR0
bits (00) condition the transmitter to attempt to interrupt only when it
is completely empty. As soon as one byte is loaded, it is no longer
empty and hence will withdraw its interrupt request.
MR0[3] – FIFO Size
Selects between 8 or 256 byte FIFO structure
MR0[2:0] – Legacy Baud Rate Group Selection
These bits are used to select one of the six-baud rate groups.
See Table 13 for the group organization.
Other combinations of MR2[2:0] should not be used
NOTE: MR0[3:0] are not used in channel B and should be set to 0.
MR0[5:4]
00
01
10
11
MR0[5:4]
00
01
10
11
000 Normal mode
001 Extended mode I
100 Extended mode II
BIT 3
FIFO Size
0 = 8 bytes
1 = 256
bytes
MR0(3)=0
MR0(3)=0
BIT 2
BAUD RATE
EXTENDED II
0 = NormaL
1 = Extend II
Interrupt Condition
8 bytes empty (Tx EMPTY)
4 or more bytes empty
6 or more bytes empty
1 or more bytes empty (TxRDY)
256 bytes empty (Tx EMPTY)
128 or more bytes empty
192 or more bytes empty
1 or more bytes empty (TxRDY)
Interrupt Condition
BIT 1
Reserved
Set to 0
SC28L202
Product data sheet
BIT 0
BAUD RATE
EXTENDED 1
0 = Normal
1 = Extend