SC28L202A1DGG,118 NXP Semiconductors, SC28L202A1DGG,118 Datasheet - Page 12

• Manufacturer Part Number: SC28L202A1DGG,118
• Description: IC UART DUAL W/FIFO 56-TSSOP
• Manufacturer: NXP Semiconductors
• Series: IMPACTr

Specifications of SC28L202A1DGG,118

• Features: False-start Bit Detection
• Number Of Channels: 2, DUART
• Fifo's: 256 Byte
• Voltage - Supply: 3.3V, 5V
• With Parallel Port: Yes
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 56-TFSOP (0.240", 6.10mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935276109118; SC28L202A1DGG-T; SC28L202A1DGG-T

Philips Semiconductors
processor. The advantageous feature of this system is the
presentation of the context of the interrupt. It is presented in both a
current interrupt register and in the interrupt vector. The context of
the interrupt shows the interrupting channel, identifies which of the
18 possible sources in requesting interrupt service and in the case
of a receiver or transmitter gives the current fill level of the FIFO.
The content of the current interrupt register also drives the Global
Registers of the interrupt system. These registers are indirect
addresses (pointers) to the interrupt source requesting service.
Programming of Bid Control Registers allows the interrupt level of
any source to be varied at any time over a range of 256 levels.
Character and Address Recognition
The character recognition system is designed as a general-purpose
system. There is one for each UART. Each recognition block stores
up to three characters. The recognition is done on a byte boundary
and sets status and interrupt when recognition events occur. Three
modes of automatic operation are provided for the in-band flow
control and three modes of automatic operation are provided for
address recognition. Both in-band flow control and address
recognition may also be completely under the control of the host
processor.
A subset of the recognition system is Xon/Xoff character recognition
and the recognition of the multi-drop address character. If Xon/Xoff
or multi-drop function is enabled the recognition system passes the
information about the recognition event to the appropriate receiver
or transmitter state machine for execution. In any case the
information about a recognition event is available to the interrupt
system and to the control processor.
Flow Control
Flow control is implemented in either the traditional RTS/CTS
protocol or in the ‘inbound’ Xon/Xoff method. Both may be controlled
by fully/partially automatic methods or by interrupt generation.
Test Modes and Software
Four test modes are provided to verify UART function and processor
interface integrity. The first three are Auto echo, Local Loop Back,
and Remote Loop Back. Through local loop back the software
developer may verify all of the interrupt, flow control; the hardware
designer verify all of the timing and pin connections. This information
is obtained without any recourse to external test equipment, logic
analyzers or terminals.
The fourth, Receiver Error Loop back verification, employs a method
of automatic checking (accounting for transmission delays) of the
transmitted data to as echoed back through the remote receiver.
Errors generate interrupt and status events.
DETAILED DESCRIPTIONS
Bus Interface
The bus interface operates in two modes selected by the I/M pin. If
this pin is HIGH the signals DACKN signal is not generated or used
and data flow to and from the chip is controlled by the state the
CEN, RDN, WRN pin combination. If the I/M pin is tied low the data
is written to the device when the DACKN pin is asserted low by the
DUART. Read data is presented by a delay from CEN active.
The Host interface is comprised of the signal pins CEN, WRN RDN,
(or R/WN) IACKN, DACKN, IRQN, 6 address pins and 8 three-state
2005 Nov 01
Dual UART
NOTE: For the convenience of the reader some paragraphs
of the following sections are repeated in descriptions of
closely linked functions described in other sections.
6
data bus pins. Addressing of the various functions of the DUART is
through the address bus A(6:0). Data is presented on the 8-bit data
bus.
DACKN Cycle
When operating in the ‘68K’ mode, bus cycle completion is indicated
by the DACKN pin (an open-drain signal) going LOW. The timing of
DACKN is controlled by GCCR[7:6] where three time delays area
available. The delay begins with the falling edge of CEN. DACKN is
presented after 1/2 to three periods of the X1/SCLK. The minimum
time will be two edges of the X1/SCLK and will be realized when the
bus cycle begins just before the transition of X1/SCLK. Usually in
this mode the address and data are set up with respect to the
leading edge of the bus cycle. Timing diagrams for this mode are
drawn with DACKN in consideration. When CEN is withdrawn before
DACKN occurs, the generation of the DACKN signal and bus cycle
will be terminated. In this case, the bus timing will return to that of
Intel type timing for that particular cycle. This timing should not be
less than the minimum read or write pulse.
The DACKN pin is an open-drain driver. At the termination of an
access to the L202 DACKN drives the pin to high impedance until
the next DACKN cycle. This will occur at the termination of the CEN
or IACKN cycle.
NOTE: The faster X86 timing may be used in the 68K mode IF the
bus cycles are faster than 1/2 period of the Sclk clock. Withdrawing
CEN before DACKN prevents the generation of DACKN. In this case
bus timing is effectively that of the X86 mode.
When operating in the ‘x86’ mode DACKN is not generated. Data is
written on the termination of CEN or WRN whichever one occurs
first. Read data is presented from the leading edge of the read
condition (CEN and RDN both low).
In the 68K mode data is written to the registers on the rise of CEN or
the fall of DACKN, whichever one occurs first. Data on a read cycle
will become valid with respect to the fall of CEN. It will always be
valid at the fall of DACKN.
IACKN Cycle, Update CIR
When the host CPU responds to the interrupt, it will usually assert
the IACKN signal low. This will cause the intelligent interrupt system
of the DUART to generate an IACKN cycle in which the condition of
the interrupting source is determined. When IACKN asserts, the last
valid of the interrupt arbitration cycle is captured in the CIR. The
value captured presents all of the important details of the highest
priority interrupt at the moment the IACKN (or the ‘Update CIR’
command) was asserted. Due to system interrupt latency the
interrupt condition captured by the CIR may not be the condition that
caused the initial assertion of the interrupt.
The Dual UART will respond to the IACKN cycle with an interrupt
vector. The interrupt vector may be a fixed value, the content of the
Interrupt Vector Register, or when ‘Interrupt Vector Modification’ is
enabled via ICR, it may contain codes for the interrupt type and/or
interrupting channel. This allows the interrupt vector to steer the
interrupt service directly to the proper service routine. The interrupt
value captured in the CIR remains until another IACKN or ‘Update
CIR’ command is given to the DUART. The interrupting channel and
interrupt type fields of the CIR set the current ‘interrupt context’ of
the DUART. The channel component of the interrupt context allows
the use of Global Interrupt Information registers that appear at fixed
positions in the register address map. For example, a read of the
Global RxFIFO will read the channel B RxFIFO if the CIR interrupt
context is channel B receiver. At another time read of the GRxFIFO
may read the channel A RxFIFO (CIR holds a channel A receiver
interrupt) and so on. Global registers exist to facilitate qualifying the
SC28L202
Product data sheet