SC28L202A1DGG,118 NXP Semiconductors, SC28L202A1DGG,118 Datasheet - Page 19

• Manufacturer Part Number: SC28L202A1DGG,118
• Description: IC UART DUAL W/FIFO 56-TSSOP
• Manufacturer: NXP Semiconductors
• Series: IMPACTr

Specifications of SC28L202A1DGG,118

• Features: False-start Bit Detection
• Number Of Channels: 2, DUART
• Fifo's: 256 Byte
• Voltage - Supply: 3.3V, 5V
• With Parallel Port: Yes
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 56-TFSOP (0.240", 6.10mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935276109118; SC28L202A1DGG-T; SC28L202A1DGG-T

Philips Semiconductors
The interrupt sources for each channel are listed below.
Transmit FIFO empty level and Receiver FIFO fill levels are unique
for each channel and may be set at any level.
Associated with the interrupt system are the interrupt mask register
(IMR) and the interrupt status register (ISR) resident in each UART.
Programming of the IMR selects which of the above sources may
enter the arbitration process. The IMR enables the interrupt. Only
the bidders in the ISR whose associated bit in the IMR is set to one
(1) will be permitted to enter the arbitration process. The ISR can be
read by the host CPU to determine all currently active interrupting
conditions. For convenience of reading the ISR the MR1 (6) bit,
when set, allows the reading of the ISR masked by the bits of the
IMR.
Enabling and Activating Interrupt sources
An interrupt source becomes enabled when writing a one to the
proper Interrupt Mask Register bit (IMR) activates its interrupt
capability. An interrupt source can never generate an IRQN or have
its ‘bid’ or interrupt number appear in the CIR unless the source has
been enabled by the appropriate bit in an IMR.
An interrupt source is active if it is presenting its bid to the interrupt
arbiter for evaluation. Most sources have simple activation
requirements. The watch-dog timer, break received, Xon/Xoff or
Address Recognition and change of state interrupts become active
when the associated events occur and the arbitration value
generated thereby exceeds the threshold value programmed in the
ICR (Interrupt Control Register).
The transmitter and receiver functions have additional controls to
modify the condition upon which the initiation of interrupt ‘bidding’
begins: the TxINT and RxINT fields of the MR0 and MR2 registers.
These fields can be used to start bidding or arbitration when the
RxFIFO is not empty, 50% full, 75% full or 100% full. For the
transmitter it is not full, 50% empty, 75% empty and empty.
Example: To increase the probability of transferring the contents of a
nearly full RxFIFO, do not allow it to start bidding until 50% or 75%
2005 Nov 01
Receiver without error
Receiver with error for each channel
Receiver Watch Dog Time-out Event
Transmitter
Change in break received status per channel
Rx loop back error
Change of state on channel input pins
Xon/Xoff character recognition
Counter-Timer
Address character recognition
No interrupt active (very useful in polled service and as a test
value to terminate interrupt service)
Dual UART
13
full. This will prevent its relatively high priority from winning the
arbitration process at low fill levels. A high threshold level could
accomplish the same thing, but may also mask out low priority
interrupt sources that must be serviced. Note that for fast channels
and/or long interrupt latency times using this feature should be used
with caution since it reduces the time the host CPU has to respond
to the interrupt request before receiver overrun occurs.
Setting interrupt priorities
The bid or interrupt number presented to the interrupt arbiter is
composed of character counts, channel codes, fixed and
programmable bit fields. The interrupt values are generated for
various interrupt sources as shown in Table 1. The value
represented by the bits 11 to 4 in Table 1 are compared against the
value represented by the ‘Threshold. The ‘Threshold’, bits 10 to 0 of
the ICR (Interrupt Control Register), is aligned such that bit 0 of the
threshold is compared to bit 1 of the interrupt value generated by
any of the sources. Whenever the value of the interrupt source is
greater than the threshold the interrupt will be generated.
The channel number arbitrates only against other channels. The
threshold is not used for the channel arbitration. This results in
channel B having the highest arbitration number. The decreasing
order is B to A. If all other parts of an arbitration cycle are equal then
the channel number will determine which channel will dominate in
the arbitration process.
Note several characteristics of Table 1 in bits 4:1. These bits contain
the identification of the bidding source as indicated below:
The codes form bits 4:1 drive part of the interrupt vector modification
and the Global Interrupt Type Register. The codes are unique to
each source type and identify them completely. The channel
numbering progresses from ‘A’ to ‘B’ as the binary numbers 0 to 1
and identify the interrupting channel uniquely. As the channels
arbitrate ‘B’ will have the highest bidding value and ‘A’ the lowest.
x001 Receiver without error
x101 Receiver with error (errors are: parity, framing and overrun.
Break is not considered an error.
x100 Receiver Watch Dog
x010 Transmitter
1110 Change of Break
1111 Rx Loop Back Error
0110 Change of State on I/O Ports
0111 Xon/Xoff Event
1000 Counter timer
1011 Address Recognition
0000 No interrupt source active
SC28L202
Product data sheet