PEB 3086 F V1.4 Infineon Technologies, PEB 3086 F V1.4 Datasheet - Page 69

• Manufacturer Part Number: PEB 3086 F V1.4
• Description: IC ISDN ACCESS CTRLR TQFP64
• Manufacturer: Infineon Technologies
• Series: ISAC™r

Specifications of PEB 3086 F V1.4

• Function: Subscriber Access Controller
• Interface: HDLC, IOM-2, ISDN, Parallel, SCI
• Number Of Circuits: 1
• Voltage - Supply: 3.3V
• Current - Supply: 30mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFQFP
• Includes: D-Channel Access Control and Priority Handler, Monitor Channel Handler, Non-Auto Mode, Transparent Mode
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEB3086FV1.4XT; PEB3086FV14NP; PEB3086FV14XP; SP000007571; SP000007572

3.4.1
The receive PLL performs phase tracking between the F/L transition of the receive signal
and the recovered clock. Phase adjustment is done by adding or subtracting 0.5 or 1
XTAL period to or from a 1.536-MHz clock cycle. The 1.536-MHz clock is than used to
generate any other clock synchronized to the line.
During (re)synchronization an internal reset condition may effect the 1.536-MHz clock to
have high or low times as short as 130 ns. After the S/T interface frame has achieved
the synchronized state (after three consecutive valid pairs of code violations) the FSC
output in TE mode is set to a specific phase relationship, thus causing once an irregular
FSC timing.
The phase relationships of the clocks are shown in
Figure 35
3.4.2
The timing extraction jitter of the ISAC-SX conforms to ITU-T Recommendation I.430
(– 7% to + 7% of the S-interface bit period).
Data Sheet
FSC
7.68 MHz
1536 kHz *
768 kHz
Description of the Receive PLL (DPLL)
Jitter
F-bit
Phase Relationships of ISAC-SX Clock Signals
* Synchronous to receive S/T. Duty Ratio 1:1 Normally
69
Chapter
Description of Functional Blocks
35.
PEB 3086
2003-01-30
ISAC-SX
ITD09664