PEB 3086 F V1.4 Infineon Technologies, PEB 3086 F V1.4 Datasheet - Page 11

• Manufacturer Part Number: PEB 3086 F V1.4
• Description: IC ISDN ACCESS CTRLR TQFP64
• Manufacturer: Infineon Technologies
• Series: ISAC™r

Specifications of PEB 3086 F V1.4

• Function: Subscriber Access Controller
• Interface: HDLC, IOM-2, ISDN, Parallel, SCI
• Number Of Circuits: 1
• Voltage - Supply: 3.3V
• Current - Supply: 30mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFQFP
• Includes: D-Channel Access Control and Priority Handler, Monitor Channel Handler, Non-Auto Mode, Transparent Mode
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEB3086FV1.4XT; PEB3086FV14NP; PEB3086FV14XP; SP000007571; SP000007572

List of Figures
Figure 78
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Data Sheet
Transmit Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Interrupt Status Registers of the HDLC Controllers . . . . . . . . . . . . . . 153
Layer 2 Test Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Register Mapping of the ISAC-SX . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Input/Output Waveform for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . 233
IOM-2 Timing (TE mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
IOM-2 Timing (LT-S, LT-T, NT mode) . . . . . . . . . . . . . . . . . . . . . . . . 235
Definition of Clock Period and Width . . . . . . . . . . . . . . . . . . . . . . . . . 236
SCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Microprocessor Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Microprocessor Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Non-Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Microprocessor Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Microprocessor Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Non-Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Sampling Time in LT-S/NT Mode (M-Bit Input) . . . . . . . . . . . . . . . . . 242
Reset Signal RES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Maximum Line Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Transformer Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
11
PEB 3086
2003-01-30
ISAC-SX
Page