PEB 3086 F V1.4 Infineon Technologies, PEB 3086 F V1.4 Datasheet - Page 137

• Manufacturer Part Number: PEB 3086 F V1.4
• Description: IC ISDN ACCESS CTRLR TQFP64
• Manufacturer: Infineon Technologies
• Series: ISAC™r

Specifications of PEB 3086 F V1.4

• Function: Subscriber Access Controller
• Interface: HDLC, IOM-2, ISDN, Parallel, SCI
• Number Of Circuits: 1
• Voltage - Supply: 3.3V
• Current - Supply: 30mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFQFP
• Includes: D-Channel Access Control and Priority Handler, Monitor Channel Handler, Non-Auto Mode, Transparent Mode
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEB3086FV1.4XT; PEB3086FV14NP; PEB3086FV14XP; SP000007571; SP000007572

All frames with valid addresses are accepted and the bytes following the address are
transferred to the m P via RFIFOx. Additional information is available in RSTAx.
Transparent mode 0 (MDS2-0 = ’110’).
Characteristics:
Every received frame is stored in RFIFOx (first byte after opening flag to CRC field).
Additional information can be read from RSTAx.
Transparent mode 1 (MDS2-0 = ’111’).
Characteristics:
A comparison is performed on the first byte after the opening flag with SAP1, SAP2 and
“group” SAPI (FE
FC
Additional information can be read from RSTAx.
Transparent mode 2 (MDS2-0 = ’101’).
Characteristics:
A comparison is performed only on the second byte after the opening flag, with TEI1,
TEI2 and group TEI (FF
case of a match the rest of the frame is stored in the RFIFOx. Additional information is
available in RSTAx.
Extended transparent mode (MDS2-0 = ’100’).
Characteristics:
In extended transparent mode fully transparent data transmission/reception without
HDLC framing is performed i.e. without FLAG generation/recognition, CRC generation/
check, bitstuffing mechanism. This allows user specific protocol variations.
Also refer to
3.8.3
3.8.3.1
The cyclic receive FIFO buffers with a length of 64 byte for D-channel and 128 byte for
B-channel have variable FIFO block sizes (thresholds) of
• 4, 8, 16 or 32 bytes for D-channel and
• 8 or 16 bytes for B-channel
which can be selected by setting the corresponding RFBS bits in the EXMx registers.
The variable block size allows an optimized HDLC processing concerning frame length,
I/O throughput and interrupt load.
The transfer protocol between HDLC FIFO and microcontroller is block oriented with the
Data Sheet
H
) for B-channel. In the case of a match, all the following bytes are stored in RFIFOx.
Data Reception
Structure and Control of the Receive FIFO
Chapter
H
/FC
no address recognition
SAPI recognition (D-channel)
High byte address recognition (B-channel)
TEI recognition (D-channel)
Low byte address recognistion (B-channel)
fully transparent
3.8.6.
H
) for D-channel, and with RAH1, RAH2 and group address (FE
H
) for D-channel, and with RAL1 and RAL2 for B-channel. In
137
Description of Functional Blocks
PEB 3086
2003-01-30
ISAC-SX
H
/